Fan-Out Package Planarization via Segmented Bonding Layer

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Solution Overview

Problem

Current integrated fan-out packaging technologies face challenges in achieving optimal planarization of the reconstitution wafer, which affects the formation of a redistribution layer and the overall reliability and routing capability of semiconductor packages.

Innovation Solution

A manufacturing method involving a carrier with a debond layer and a bonding layer, where dies are bonded using a dielectric adhesive layer, followed by the formation of conductive pillars and a redistribution layer, allowing for precise planarization and improved adhesion, enabling efficient routing and packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional integrated fan-out packaging is used, then compactness is achieved, but planarization of the reconstitution wafer is insufficient, affecting redistribution layer formation

Engineering Contradiction:
Improveplanarization of reconstitution waferVSAvoidpackaging process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The packaging process is divided into distinct stages: forming the bonding layer with adhesive regions, bonding dies at wafer level, and subsequent planarization steps. This segmentation allows each stage to be optimized independently, with the bonding layer structure specifically designed to facilitate planarization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bonding layer is pre-formed with specific adhesive regions before die bonding occurs. This preliminary structuring of the bonding layer with varying adhesive properties enables controlled die attachment and subsequent planarization, addressing the planarization challenge before redistribution layer formation.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If wafer level packaging is used, then productivity is improved, but adhesion between dies and substrate may be insufficient

Engineering Contradiction:
Improvepackaging throughputVSAvoidadhesion strength
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bonding layer is designed with non-uniform adhesive characteristics, having first adhesive regions with different properties than second adhesive regions. This local variation in adhesive quality allows optimization for both wafer-level processing efficiency and reliable die attachment, enabling productivity and reliability to coexist.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bonding layer functions as a composite structure combining materials with different adhesive properties in specific regions. This composite approach enables the bonding layer to provide both the mechanical support needed for wafer-level handling and the adhesive strength required for reliable die attachment.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the planarization and adhesion processes, resulting in improved reliability and routing capabilities for semiconductor packages, addressing the limitations of existing technologies.

Implementation Method 1

a bonding layer (116) disposed on the debond layer (114)... a die (120) disposed on the bonding layer (116)... a dielectric adhesive layer covering a portion of the active surface of the die and a portion of the bonding layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS20190139925A1Package structure and manufacturing method thereof
Publication Date: 2019.05.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20190139925A1 patent drawing
  • US20190139925A1 patent drawing
  • US20190139925A1 patent drawing

AI summary

A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is encapsulated in the insulating encapsulation. The redistribution layer is located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip. The bonding layer mechanically connects the redistribution layer and the at least one first chip.