Fan-Out Package Structure With Asymmetric Layers for Warpage Control
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving smaller, more integrated, and reliable package structures that can accommodate advanced semiconductor devices while maintaining manufacturing efficiency and reducing warpage and thermal expansion issues.
Innovation Solution
A package structure with fan-out features is developed, utilizing a redistribution structure with insulating and conductive layers, conductive vias, and asymmetric protective layers with varying thermal expansion coefficients to reduce thickness and warpage, and incorporating stiffener elements for stability during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging technologies are used, then package protection and connection interface functions are provided, but package size and height cannot be reduced further
Solution Approach 1:
The patent transitions from conventional two-dimensional packaging layouts to three-dimensional stacked architectures, where semiconductor dies are vertically stacked above substrate pads. This dimensional change enables significant reduction in package footprint area while maintaining or improving connectivity functions through vertical interconnections and redistribution layers.
Solution Approach 2:
The patent implements nested structures where semiconductor dies are stacked vertically above substrate pads, with redistribution layers and protective layers nested between and around components. This nesting approach maximizes space utilization, enabling smaller package size while maintaining all necessary functional elements.
2Area of stationary object
If package size is reduced, then density improves, but warpage and thermal expansion issues worsen
Solution Approach 1:
The patent applies different material properties to different regions of the package structure. Protective layers with specific thermal expansion coefficients are selectively positioned, and stiffener elements are strategically placed in high-stress areas. This local differentiation of material properties compensates for thermal expansion and reduces warpage in the compacted package structure.
Solution Approach 2:
The patent employs composite material structures including multiple protective layers with varying thermal expansion coefficients, combinations of dielectric and conductive materials in redistribution layers, and integrated stiffener elements. These composite structures provide thermal management and mechanical stability while maintaining reduced package area.
3Quantity of substance
If integration density is increased, then functional density improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the packaging structure into distinct functional layers including substrate pads, semiconductor dies, redistribution layers, protective layers, and stiffener elements. This segmentation allows each component to be manufactured and tested separately before assembly, reducing overall manufacturing complexity despite high integration density.
Solution Approach 2:
The patent designs multi-functional components that perform multiple roles: redistribution layers provide both electrical connectivity and structural support, protective layers offer both mechanical protection and thermal management, and stiffener elements provide both structural rigidity and warpage control. This multi-functionality reduces the total number of components needed, simplifying manufacturing while achieving high functional density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of thinner, more reliable semiconductor packages with improved electrical connectivity and reduced warpage, enhancing manufacturing yield and reliability.
Implementation Method 1
asymmetric protective layers with varying thermal expansion coefficients to reduce thickness and warpage
Implementation Method 2
redistribution structure with insulating and conductive layers, conductive vias
Data Source
AI summary
A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.