Fan-Out Semiconductor Packaging with Structured Dielectric Layer
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Solution Overview
Problem
The high cost and complexity of packaging semiconductor chips in semiconductor device manufacturing, which includes protecting them from environmental and physical stresses while allowing for electrical signal transmission and heat removal, pose a challenge for manufacturers aiming to increase performance while reducing costs.
Innovation Solution
A method involving the use of carriers with semiconductor chips, a dielectric layer, and metal layers to create fan-out type packages, where the dielectric layer is structured to expose chip electrodes and filled with conductive material, allowing for redistribution and increased contact area, thereby simplifying the packaging process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging methods are used to protect semiconductor chips and enable electrical signal transmission, then reliability and functionality are improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent combines multiple packaging functions into a single integrated structure. The package substrate integrates electrical connection elements, mechanical support, and heat dissipation pathways in one component, eliminating the need for separate packaging elements and reducing overall complexity while maintaining protection and functionality
Solution Approach 2:
The package substrate serves multiple functions simultaneously: it provides mechanical support for the semiconductor chip, establishes electrical connections through integrated connection elements, enables heat dissipation through thermal pathways, and offers environmental protection. This multi-functionality reduces the number of separate components needed
2Reliability
If traditional packaging methods are used to protect semiconductor chips and enable electrical signal transmission, then reliability and functionality are improved, but manufacturing cost increases
Solution Approach 1:
The package substrate is prepared in advance with pre-formed electrical connection elements and thermal pathways before the semiconductor chip is attached. This preliminary preparation simplifies the final assembly process and reduces manufacturing steps, thereby lowering costs while ensuring reliable connections
Solution Approach 2:
The patent modifies material properties and structural parameters of the package substrate to achieve both protection and cost-effectiveness. By optimizing material selection and structural design parameters, the solution maintains reliability requirements while reducing manufacturing complexity and cost
Data Source
AI summary
One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.