Fan-Out Semiconductor Package with Redistribution Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor package technologies face challenges in mounting small-sized semiconductor chips with a large number of I/O terminals due to spatial limitations and reliability issues such as cracking and peeling caused by thermal and mechanical stress, particularly in fan-in packages which require redistribution of I/O terminals inside the chip.
Innovation Solution
A semiconductor package design that includes a connection structure with insulating layers and redistribution layers, encapsulating the semiconductor chip, and surface mount components with through-holes and connection vias to reduce stress and enhance reliability, allowing for the redistribution of I/O terminals outside the chip, enabling a compact and reliable fan-out package that can be directly mounted on a mainboard without an interposer substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fan-in package technology is used to redistribute I/O terminals inside the chip, then spatial utilization is improved, but thermal and mechanical stress concentration causes cracking and peeling reducing reliability
Solution Approach 1:
The patent inverts the traditional fan-in approach by redistributing I/O terminals outside the chip in a fan-out configuration. The connection structure includes insulating layers and redistribution layers with connection vias that route signals from the chip surface to external pads, eliminating the need for dense internal redistribution and reducing stress concentration on the chip.
Solution Approach 2:
The patent transitions from planar in-chip redistribution to three-dimensional external redistribution using multiple insulating layers and connection vias. The connection structure extends vertically with insulating layers stacked above each other, allowing I/O terminals to be redistributed in the vertical dimension rather than confined to the chip surface plane.
2Reliability
If surface mount components are added to improve electrical performance, then noise and impedance are reduced, but thermal and mechanical stress increases causing cracks in solder connections
Solution Approach 1:
The patent introduces connection vias and connection metals as intermediary structures between the chip and surface mount components. These intermediaries provide robust mechanical and electrical connections that can withstand thermal and mechanical stress, preventing cracks in the solder connections while maintaining improved electrical performance from the surface mount components.
3Area of stationary object
If compact size is achieved with multiple pins, then spatial efficiency is improved, but stress concentration on outer pad areas increases causing reliability defects
Solution Approach 1:
The patent applies local quality by creating distinct regions within the pads: first regions corresponding to areas adjacent to each other and second regions corresponding to remaining portions. Connection vias are strategically positioned to overlap with the first regions, providing localized reinforcement where stress concentration occurs, while maintaining the compact overall package size.
Data Source
AI summary
A semiconductor package includes: a connection structure including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip having connection pads connected to the redistribution layer; an encapsulant encapsulating the semiconductor chip; first and second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in regions of the first and second pads; first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.