Fan-Out Stacked Semiconductor Packaging Without Circuit Substrates
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Solution Overview
Problem
Traditional substrate manufacturing for printed circuit boards is limited by the number of layers and line width/spacing, which cannot support the increasing integration levels of modern semiconductor chips, and advanced packaging methods are costly and time-consuming.
Innovation Solution
A fan-out stacked semiconductor package structure that combines a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip system-in-package unit, using rewiring layers and wire bonding to eliminate the need for circuit substrates, allowing for high-density and high-integration packaging with reduced line width/spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional substrate manufacturing is used to support electronic components, then the structure is simple and easy to manufacture, but the number of substrate layers is limited to within 12 and the line width/line spacing cannot be reduced below 20 μm/20 μm, which cannot support higher integration levels
Solution Approach 1:
The patent transitions from traditional 2D substrate manufacturing to 2.5D fan-out wafer level packaging and 3D stacked packaging. By adding vertical dimension with multiple packaging layers and stacking memory chips vertically, the design achieves higher integration density while reducing line width/line spacing requirements. The fan-out structure redistributes signals in the horizontal plane, enabling finer pitch connections.
Solution Approach 2:
The patent implements nested packaging structures where memory chips are stacked vertically within a packaging substrate, and multiple packaging layers are nested together. The first packaging substrate contains memory chips, which are then stacked with additional packaging substrates containing peripheral circuit chips. This nested arrangement achieves high integration without requiring proportionally larger substrate areas or thicker individual layers.
2Adaptability or versatility
If more chip I/Os are integrated, then the functionality and integration level increase, but the number of substrate layers increases beyond 12 and manufacturing cost increases
Solution Approach 1:
The patent segments the integrated circuit system into distinct functional modules packaged separately and then interconnected. Memory chips are packaged in one substrate while peripheral circuit chips are packaged in another substrate. These segmented packages are then connected through wire bonding or other interconnection techniques. This segmentation allows each module to be optimized independently for its function while reducing overall manufacturing complexity compared to integrating everything on a single large substrate.
Solution Approach 2:
The packaging substrate acts as an intermediary carrier that enables connection between chips without requiring direct integration on a single substrate. The substrate provides ball grid arrays and wire bonding structures that mediate the electrical connections between memory chips and peripheral circuit chips. This intermediary approach simplifies manufacturing by allowing separate chip fabrication and packaging processes to be combined through standardized interconnection interfaces.
3Manufacturing precision
If advanced packaging methods such as 2.5D & fan-out wafer level advanced packaging are used, then higher integration is achieved, but the manufacturing cost increases and manufacturing time increases
Solution Approach 1:
The patent performs preliminary packaging of memory chips and peripheral circuit chips on separate substrates before final assembly. Wire bonding and other interconnections are established in advance on each substrate independently. This preliminary action allows parallel processing of different chip modules, reducing overall manufacturing time compared to sequential assembly. The pre-packaged modules are then stacked and interconnected, achieving high integration without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent merges multiple packaging processes into a unified stacked package structure. Memory chip packages and peripheral circuit chip packages are combined vertically in a single assembly. The fan-out structure merges signal redistribution with the packaging substrate itself, eliminating the need for separate interconnection substrates. This merging of functions into a single integrated package structure reduces the total number of manufacturing steps and improves productivity compared to separate packaging approaches.
Data Source
AI summary
A fan-out stacked semiconductor package structure and a packaging method thereof are disclosed. The structure includes a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit. The three-dimensional memory chip package unit includes: at least two memory chips laminated in a stepped configuration; a first rewiring layer; wire bonding structures, each of which being electrically connected to the bonding pad and the first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The two-dimensional fan-out peripheral circuit chip SiP package unit includes: a second rewiring layer; at least one peripheral circuit chip; a third rewiring layer, bonded to the peripheral circuit chip; metal connection pillars; a second encapsulating layer, encapsulating the peripheral circuit chip and the metal connection pillars; and second metal bumps, formed on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer.