Wafer-Level Fan-Out Packaging Structure for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wafer level fan out semiconductor devices suffer from warpage and solder ball detachment due to thermal expansion or shrinkage, and they require improved packaging techniques to enhance heat dissipation efficiency.
Innovation Solution
The semiconductor device incorporates a first sealing part with a thermal expansion coefficient similar to the second sealing part, which encapsulates the semiconductor die and redistribution layers, and a second sealing part that locks the solder balls to the redistribution layers, minimizing warpage and detachment, while exposing the second surface of the semiconductor die for enhanced heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional wafer level fan out semiconductor device structure is used, then manufacturing is simplified, but warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent modifies the thermal expansion coefficient parameter of the sealing part material to match that of the semiconductor die. By selecting a sealing part material whose thermal expansion coefficient is substantially equal to that of the semiconductor die, the invention eliminates warpage caused by thermal expansion mismatch while maintaining the simplified wafer-level manufacturing process.
Solution Approach 2:
The patent achieves homogeneity in thermal expansion properties between different components (semiconductor die and sealing part). This material property matching ensures uniform thermal behavior across the device structure, preventing differential expansion and the resulting warpage during temperature cycling.
2Device complexity
If conventional sealing structure is used, then device structure is simple, but solder balls detach during thermal expansion or shrinkage
Solution Approach 1:
The patent transitions from a conventional planar sealing structure to a three-dimensional recessed sealing configuration. The sealing part forms a recess that receives and mechanically interlocks with the solder balls, creating a multi-dimensional constraint system that prevents solder ball detachment during thermal cycling while adding minimal structural complexity.
Solution Approach 2:
The patent utilizes the spherical geometry of solder balls by designing a recessed sealing structure that conforms to their curved surfaces. The recessed configuration provides optimal contact and mechanical interlocking with the spherical solder balls, enhancing attachment reliability during thermal expansion and shrinkage.
3Shape
If semiconductor die second surface is covered, then device structure is complete, but heat dissipation efficiency is reduced
Solution Approach 1:
The patent segments the sealing function from the heat dissipation function. The sealing part is divided into a recessed portion that contacts the solder balls and a non-recessed portion that exposes the semiconductor die's second surface. This segmentation allows the device to maintain structural completeness while providing direct thermal pathways for efficient heat dissipation from the die's active surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses warpage and solder ball detachment, while maximizing heat dissipation efficiency by using materials with matching thermal expansion coefficients and securing the solder balls to the redistribution layers.
Implementation Method 1
a first and a second sealing parts having the same thermal expansion coefficient
Implementation Method 2
solder balls may be easily detached during thermal expansion or shrinkage
Implementation Method 3
exposing the semiconductor die's second surface for enhanced heat dissipation
Data Source
AI summary
A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.