Fan-Out Chip Packaging Heterogeneous Integration
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Solution Overview
Problem
Existing fan-out chip packaging technologies face challenges in effectively packaging and interconnecting semiconductor chips with initial bumps and those without initial bumps.
Innovation Solution
A packaging method involving a first chip with solder bumps and a second chip without solder bumps, where a first dielectric layer is formed on the second chip with through-holes, bonded to a carrier, and packaged with the first chip, followed by deposition of a second dielectric layer and a metal redistribution layer to achieve electrical interconnection, along with under-bump metallization and micro-bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing fan-out chip packaging technologies are used, then chips without initial bumps can be packaged, but chips with initial bumps cannot be effectively packaged or interconnected
Solution Approach 1:
The patent introduces a carrier as an intermediary substrate that receives both chips with bumps and chips without bumps. The carrier provides a common bonding interface (bonding layer) that mediates the connection between different chip types, enabling heterogeneous integration while maintaining reliable interconnections through the standardized carrier interface.
Solution Approach 2:
The carrier structure serves multiple functions: it acts as a bonding substrate for both bumped and non-bumped chips, provides mechanical support during packaging, enables redistribution of electrical connections through RDL layers, and facilitates the integration of different chip types. This multi-functionality resolves the contradiction by making the packaging system universally applicable to various chip configurations.
2Productivity
If a unified packaging method is developed for both chips with and without initial bumps, then packaging efficiency is improved, but the complexity of the packaging process increases
Solution Approach 1:
The packaging process is segmented into distinct stages: chip preparation stage (where chips with and without bumps are separately prepared), carrier bonding stage (where both chip types are bonded to the carrier using the same bonding layer process), and interconnection stage (where RDL and bumping processes are applied). This segmentation allows different chip types to be processed differently where needed while using unified processes where possible, improving efficiency without excessive complexity.
Solution Approach 2:
The carrier and bonding layer are prepared in advance before chip attachment. This preliminary action establishes a standardized interface that simplifies subsequent chip bonding operations. By pre-configuring the carrier with bonding layers and RDL structures, the method enables efficient processing of both chip types through a unified workflow, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables effective integration and interconnection of chips with and without initial bumps, enhancing packaging efficiency and applicability in semiconductor packaging.
Implementation Method 1
providing a carrier with a bonding layer formed on a surface thereof, and bonding the first chip and the second chip to the bonding layer
Implementation Method 2
packaging the first chip and the second chip, wherein the bumps of the first chip and the through-holes of the first dielectric layer on the surface of the second chip are exposed after the package
Implementation Method 3
depositing a second dielectric layer covering the first chip and the second chip
Implementation Method 4
depositing a second dielectric layer covering the first chip and the second chip
Implementation Method 5
fabricating a metal redistribution layer aligned to the windows to achieve electrical interconnection of the first chip and the second chip
Implementation Method 6
an exposure method is adopted for decreasing adhesiveness of the UV bonding adhesive to achieve a separation of the UV bonding adhesive from a plastic packaging material
Data Source
AI summary
A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.