Fan-Out Package Interconnect Layout for Accurate Chip Alignment
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Solution Overview
Problem
Current methods for preparing inter-chip fine interconnection lines in fan-out packages face high costs and challenges in controlling silicon wafer embedding and spacing position accuracy, leading to difficulties in chip mounting and alignment.
Innovation Solution
A manufacturing method involving a temporary carrier, strippable material, redistribution layer, and self-aligning mounting technology to form inter-chip fine internal interconnection lines, eliminating the need for silicon bridges and ensuring accurate chip alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon bridge embedding method is used to prepare inter-chip fine interconnection line, then electrical interconnection between chips is achieved, but mounting position accuracy and spacing position accuracy cannot be controlled, leading to alignment difficulties
Solution Approach 1:
The patent introduces a carrier as an intermediary substrate that pre-carries the fine interconnection lines. This carrier serves as a mediator between the chip mounting process and the interconnection formation, enabling precise positioning of chips relative to the interconnection lines while maintaining reliable electrical connections. The carrier's structured design with positioning features ensures both mounting accuracy and spacing control.
2Reliability
If silicon bridge embedding method is used, then inter-chip interconnection is achieved, but the process cost increases and manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the fine interconnection lines and their positioning structures on the carrier before chip mounting. This advance preparation eliminates the need for complex post-mounting alignment and interconnection formation steps, reducing overall manufacturing complexity and cost while ensuring reliable inter-chip interconnection.
3Ease of manufacture
If traditional fan-out package method is used, then chip packaging is achieved, but spacing position accuracy between chips cannot be controlled
Solution Approach 1:
The patent applies local quality by incorporating specific positioning structures and spacing features at critical locations on the carrier. These localized structural features ensure precise spacing control between chips at their mounting positions while maintaining overall processability of the packaging operation. The carrier's design provides local precision where needed without compromising global manufacturability.
Data Source
AI summary
Provided are a fan-out package structure and a manufacturing method thereof. The fan-out package structure provided in the embodiments of the present disclosure, and the fan-out package structure obtained by the manufacturing method provided in the embodiments of the present disclosure have an inter-chip fine interconnection line between functional surfaces of chips, so that fine interconnection pin pads of adjacent chips form electrical interconnection.