Fan-Out Package Embedding Passive Components
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing size and thickness while integrating multiple passive components with semiconductor chips, leading to increased manufacturing costs and defect rates due to thickness deviations and spatial limitations.
Innovation Solution
A fan-out semiconductor package design that incorporates a first connection member with through-holes and redistribution layers, allowing passive components to be embedded within the chip, and a second connection member that redistributes connection pads to a larger area, eliminating the need for an interposer substrate and reducing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive components are mounted together with semiconductor chip in conventional packages, then functional integration is improved, but package size and thickness increase
Solution Approach 1:
The patent embeds passive components directly within the semiconductor chip structure by forming them in the same semiconductor substrate. The passive components are created by depositing conductive patterns and dielectric layers within the chip itself, nesting multiple functional elements (active and passive) within a single integrated structure, thereby achieving high functional integration without increasing package volume.
Solution Approach 2:
The patent utilizes three-dimensional stacking and vertical integration within the semiconductor chip. Connection terminals are redistributed from a planar arrangement to a fan-out configuration that extends in multiple dimensions, allowing passive components to be positioned at different vertical levels and horizontal positions within the chip volume, maximizing space utilization without increasing overall package size.
2Adaptability or versatility
If multiple passive components are integrated with semiconductor chip, then functionality is improved, but manufacturing complexity and defect rate increase
Solution Approach 1:
The patent combines the manufacturing processes for passive components and semiconductor circuits into a single integrated fabrication sequence. Conductive patterns for both passive components and active circuits are formed simultaneously using the same deposition and lithography processes. Dielectric layers are deposited uniformly across the entire substrate, creating both passive component structures and circuit interconnects in one manufacturing run, thereby reducing process complexity despite increased functional integration.
3Adaptability or versatility
If connection terminals are redistributed outwardly to increase pin count, then connectivity is improved, but package thickness increases
Solution Approach 1:
The patent implements fan-out redistribution by extending connection terminals from the chip surface into the surrounding encapsulant material in a controlled manner. The terminals are redistributed in a three-dimensional space rather than simply extending linearly, allowing multiple connection points to be accessed within a compact vertical profile. This dimensional redistribution enables increased connectivity while maintaining thin package thickness.
4Volume of moving object
If package size is reduced to meet miniaturization demands, then compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the fabrication of passive components and semiconductor circuits into a single integrated process that occurs at the same manufacturing stage. By forming all structures (conductive patterns, dielectric layers, passive component electrodes) simultaneously on the same substrate using standardized semiconductor fabrication equipment, the patent achieves compact integration without requiring additional precision steps or specialized manufacturing processes.
Data Source
AI summary
A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.