Fan-Out Semiconductor Package Grinding Copper Burring Prevention

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Solution Overview

Problem

The existing fan-out semiconductor packages face challenges with copper burring during the grinding process, leading to foreign materials and electrical shorts, which affect processability and reliability.

Innovation Solution

A fan-out semiconductor package design featuring a frame with a blind recess portion and metal bumps on both the semiconductor chip and the wiring layer, where the metal bumps are exposed during grinding, preventing excessive copper residue and improving processability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a grinding process is used to flatten the semiconductor package, then the surface flatness is improved, but copper burring and foreign materials are generated affecting reliability

Engineering Contradiction:
Improvesurface flatnessVSAvoidelectrical connection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent extracts the copper layer from the grinding area by forming a recess portion that exposes only the metal bump surfaces during grinding. This prevents copper burring generation while maintaining surface flatness, as the grinding wheel only contacts the metal bumps rather than the copper wiring layers.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary action by forming metal bumps on the wiring layers before the grinding process. These metal bumps serve as protective elements that prevent copper burring during subsequent grinding operations, as they are positioned to be exposed during grinding while the copper layers remain protected.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If metal bumps are formed on wiring layers and exposed during grinding, then copper burring is reduced, but the device structure becomes more complex

Engineering Contradiction:
ImproveprocessabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by designing the metal bumps to serve multiple purposes: they act as electrical connection elements, protective elements during grinding, and reference surfaces for flatness control. This reduces the need for separate protective structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the protective function with the electrical connection function by using the same metal bump structure for both purposes. The metal bumps that provide electrical connectivity also serve as the exposed surfaces during grinding, eliminating the need for separate protective layers or structures.

Inventive Principle:
Principle #5Merging (Combining)

3Volume of moving object

If connection terminals are redistributed outwardly of the semiconductor chip region, then compact size is achieved, but copper burring and foreign materials affect manufacturing precision

Engineering Contradiction:
Improvepackage sizeVSAvoidgrinding process precision
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent extracts the copper wiring layers from the grinding zone by designing a recess portion that exposes only metal bumps during grinding. This prevents copper burring and foreign material generation while maintaining the compact fan-out package structure with redistributed connection terminals.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary action by forming metal bumps on the wiring layers before redistribution and grinding processes. These pre-formed metal bumps ensure that during subsequent grinding operations, only the metal bump surfaces are contacted, preventing copper contamination while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10504825B2Fan-out semiconductor package
Publication Date: 2019.12.10 SAMSUNG ELECTRONICS CO LTD
  • US10504825B2 patent drawing
  • US10504825B2 patent drawing
  • US10504825B2 patent drawing

AI summary

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps.