Fan-Out Semiconductor Package with 3D Redistribution for I/O Spacing
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Solution Overview
Problem
The increased integration and miniaturization of semiconductor devices lead to reduced intervals between input/output (I/O) terminals, causing interference issues that existing fan-out semiconductor packages struggle to address effectively.
Innovation Solution
A semiconductor package design featuring a first redistribution structure with tapered redistribution vias, a wetting layer, and a through electrode, along with a second redistribution structure, to increase I/O terminal spacing and improve electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of I/O terminals is increased to meet performance requirements, then data processing capability is improved, but interference between I/O terminals occurs due to reduced intervals
Solution Approach 1:
The patent transitions from a planar arrangement of I/O terminals to a three-dimensional stacked configuration using multiple redistribution layers. Through-electrodes penetrate vertically through the molding layer to establish electrical connections across different layers, effectively moving terminal connections from a two-dimensional plane to a three-dimensional space, thereby increasing spacing between terminals while maintaining high I/O density
Solution Approach 2:
The patent divides the semiconductor package into multiple functional layers including first and second redistribution layers, a molding layer, and through-electrodes. This segmentation allows I/O terminals to be distributed across different spatial layers, increasing the effective spacing between terminals and reducing electromagnetic interference while maintaining high connectivity
2Volume of moving object
If the size of semiconductor packages is reduced for miniaturization, then package size is decreased, but reliability of electrical connections deteriorates
Solution Approach 1:
The patent implements a nested structure where through-electrodes are embedded within the molding layer, which itself is surrounded by redistribution layers. This nested configuration allows multiple functional elements to be compactly arranged within a small volume while maintaining reliable electrical connections through the vertically extended through-electrodes that penetrate the molding layer
Solution Approach 2:
The patent utilizes vertical dimensionality through through-electrodes that extend perpendicular to the package surface, allowing electrical connections to be established in the third dimension. This vertical connection approach enables compact horizontal packaging while maintaining connection reliability through the extended vertical path of the through-electrodes
3Object-affected harmful factors
If through-electrodes are formed to extend through the molding layer, then I/O terminal spacing is increased, but formation complexity increases due to需要通过 precise positioning and deep etching
Solution Approach 1:
The patent forms through-electrodes and establishes their precise positions within the molding layer during the package formation process itself, rather than as a subsequent step. This preliminary integration of through-electrode formation into the molding process allows for precise positioning to be established upfront, simplifying subsequent assembly steps while ensuring adequate I/O terminal spacing
Data Source
AI summary
A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.