Fan-Out Semiconductor Package With Multi-Stage Conductors
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Solution Overview
Problem
Current fan-out semiconductor packages face limitations in thinness and reliability due to the use of interposer substrates, which increase costs and lead to signal loss and warpage issues when stacking multiple memory chips, and wire bonding for electrical connections results in long signal paths.
Innovation Solution
A fan-out semiconductor package design that stacks semiconductor chips in a through-hole with multi-stage conductors of different heights, eliminating the need for interposer substrates and using redistribution layers for electrical connections, thereby reducing thickness and signal path length and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposer substrates are used for stacking multiple memory chips, then electrical connections can be established, but package thickness increases and signal loss occurs
Solution Approach 1:
The patent removes the interposer substrate from the package structure entirely. Instead of using a separate interposer substrate to facilitate electrical connections between stacked memory chips, the invention directly connects chips through redistribution layers formed on the chip surfaces, eliminating the thickness contribution and signal loss associated with the interposer substrate
Solution Approach 2:
The patent combines the functions of the interposer substrate and redistribution layers into a single integrated structure. The redistribution layers are formed directly on the memory chip surfaces and provide both the electrical connection function and the redistribution function that would otherwise require a separate interposer substrate, thereby reducing package thickness
2Reliability
If wire bonding is used for electrical connections, then connections can be established, but signal path length increases causing signal loss
Solution Approach 1:
The patent replaces the mechanical wire bonding process with a planar redistribution layer structure. Instead of using physical wires to connect chips, the invention uses conductive redistribution layers formed through photolithography and etching processes, creating short, controlled signal paths that eliminate the long signal paths associated with wire bonding
Solution Approach 2:
The patent transitions from three-dimensional wire bonding connections to two-dimensional planar redistribution layer connections. The electrical connections are established through conductive patterns formed on the chip surfaces, reducing signal path length by eliminating the vertical wire loops and creating direct, short signal routes
3Quantity of substance
If multiple memory chips are stacked, then storage capacity increases, but warpage issues and signal loss occur
Solution Approach 1:
The patent applies different structural characteristics to different regions of the package. The redistribution layers are strategically positioned and dimensioned to provide local reinforcement and stress distribution, preventing warpage in specific areas while maintaining the stacked chip structure for increased storage capacity
Solution Approach 2:
The patent employs composite material structures in the redistribution layers and encapsulant to manage thermal expansion differences and mechanical stresses between stacked chips. The combination of different materials with complementary properties reduces warpage while maintaining the multi-chip stack for increased storage capacity
Data Source
AI summary
A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.