Fan-Out Semiconductor Package Structure with Redistribution Layer
Solution Overview
Problem
Current semiconductor package technologies are limited by low I/O connection numbers and high manufacturing costs, particularly in high-end devices, due to the constraints of wafer level fan-in packages.
Innovation Solution
A semiconductor package structure and manufacturing method that incorporates a redistribution structure with a first and second encapsulant, allowing for higher I/O connections through a fan-out configuration, replacing the need for a through silicon via (TSV) interposer and reducing manufacturing costs by forming the redistribution layer and structure separately during different processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer level fan-in package is used, then manufacturing cost is reduced, but I/O connection number is limited to low-end devices (200-300 connections)
Solution Approach 1:
The patent transitions from a fan-in configuration to a fan-out configuration, fundamentally changing the dimensional arrangement of I/O connections. The die is embedded in the first encapsulant with I/O terminals routed outward through redistribution layers, expanding connections from a limited surface area to a broader distributed pattern that supports thousands of I/O connections while maintaining cost-effectiveness
Solution Approach 2:
The patent divides the package structure into distinct functional layers: the die, first encapsulant, redistribution layer, and second encapsulant. This segmentation allows independent optimization of each layer, enabling the redistribution layer to expand I/O connections across a larger area while the encapsulants provide protection and structural support, thereby achieving high I/O counts without proportionally increasing manufacturing complexity
2Adaptability or versatility
If through silicon via (TSV) interposer is used to achieve higher I/O connections, then I/O connection number increases, but manufacturing cost increases
Solution Approach 1:
The patent replaces the expensive TSV interposer with a cost-effective organic substrate that serves the same functional purpose of redistributing I/O connections. The organic substrate, while less durable than silicon, achieves the required I/O expansion at significantly lower manufacturing cost, making high I/O connections accessible for applications that do not require the extreme performance of TSV technology
Solution Approach 2:
The patent creates a functional equivalent of the TSV interposer using conventional organic substrate technology with redistribution layers. Instead of copying the silicon-based TSV structure, it replicates the I/O redistribution function using cheaper materials and processes, achieving similar connectivity outcomes without the high manufacturing costs associated with TSV fabrication
3Ease of manufacture
If redistribution layer and redistribution structure are formed in the same process, then manufacturing is simplified, but warpage level increases
Solution Approach 1:
The patent separates the formation of the redistribution layer and redistribution structure into distinct manufacturing stages. The redistribution layer is first formed on the die, then the die is embedded in the first encapsulant, and finally the redistribution structure is formed on the encapsulated assembly. This segmentation allows each stage to be optimized independently and reduces cumulative warpage that would result from forming both elements in a single high-stress process
4Adaptability or versatility
If fan-out configuration is implemented, then I/O connection number increases, but structure complexity increases
Solution Approach 1:
The patent designs the encapsulants to serve multiple functions simultaneously: providing mechanical protection for the die, enabling thermal management through heat dissipation pathways, facilitating electrical isolation between different I/O groups, and supporting the redistribution layer structure. This multi-functionality reduces the need for additional specialized components, thereby managing overall structural complexity while achieving high I/O connection counts
Data Source
AI summary
A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.