Fan-out Semiconductor Package With Varying Insulating Layer Thickness
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Solution Overview
Problem
Current fan-in semiconductor packages face challenges in accommodating a large number of I/O terminals and compact size requirements, leading to spatial limitations and difficulties in direct mounting on electronic device main boards, especially when the size and pitch of I/O terminals are insufficient for standard ball layouts.
Innovation Solution
A fan-out semiconductor package design with varying thicknesses of insulating and via layers, allowing for redistribution of connection pads outwardly from the semiconductor chip, enabling a standardized ball layout and improved board level reliability through stress dispersion, thus facilitating direct mounting on electronic device main boards without the need for interposer substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If connection terminals are redistributed outwardly to increase the number of I/O terminals, then the I/O capacity is improved, but the package size increases and spatial limitations occur
Solution Approach 1:
The patent applies dimensional change by transitioning from a planar redistribution layout to a three-dimensional multilayer structure. Multiple redistribution layers are stacked vertically with via holes connecting them, allowing I/O terminals to be distributed across multiple layers rather than spreading out horizontally. This enables increased I/O capacity while maintaining a compact package footprint by utilizing the vertical dimension for terminal redistribution.
2Ease of manufacture
If uniform thickness insulating layers are used in redistribution layers, then manufacturing is simplified, but stress concentration occurs leading to cracks and reliability issues
Solution Approach 1:
The patent implements local quality by varying the thickness of insulating layers at different locations within the redistribution structure. Specifically, the first insulating layer has a first thickness and the second insulating layer has a second thickness different from the first. This non-uniform thickness distribution allows stress to be dispersed throughout the structure rather than concentrated at interfaces between layers of identical thickness, thereby preventing cracks and improving board-level reliability while maintaining manufacturability.
3Area of stationary object
If connection terminals are kept compact on the chip, then package size is reduced, but direct mounting on main boards becomes difficult due to insufficient pitch
Solution Approach 1:
The patent enables direct mounting on main boards by utilizing vertical stacking of multiple redistribution layers with varying thicknesses. This three-dimensional arrangement allows connection terminals to be positioned at different heights and horizontal locations, creating a fan-out pattern that provides sufficient pitch for standard ball layouts while maintaining a compact overall package size. The multilayer structure bridges the gap between compact chip dimensions and board-mounted terminal requirements.
Data Source
AI summary
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.