3D Fan-Out Packaging Frame for Warpage-Stable Chip Stacking
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Solution Overview
Problem
Current 3D packaging technologies face challenges such as high costs, low yields, warpage issues, and structural instability due to mold flow during encapsulation, especially in fan-out panel-level processes, limiting the integration of high IO and fine pitch RDL.
Innovation Solution
A three-dimensional stacking fan-out packaging device utilizing a pre-supported electrical connection frame to define a concave chip bonding area, with staggered and symmetrically arranged chips, and a coreless RDL structure, eliminating the need for on-site slotting and electroplating, and ensuring structural stability through a symmetric coreless RDL design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fan-out technology forms packaging body after chip stacking and uses electroplating after slotting, then connection between distribution layers can be realized, but mold flow causes significant chip displacement affecting structure stability and performance
Solution Approach 1:
The patent applies preliminary action by pre-forming the electrical connection frame with conductive posts and distribution layers before chip stacking. This allows the connection structure to be established in advance, eliminating the need for post-stack slotting and electroplating, thereby preventing chip displacement during mold flow while maintaining structural stability.
2Quantity of substance
If TSV direct stacking method is used for HBM packaging, then high capacity can be achieved, but cost accounts for nearly 30% and yield control is difficult
Solution Approach 1:
The patent extracts the expensive TSV process from the packaging methodology by using fan-out wafer-level packaging with pre-formed electrical connection frames instead of through-silicon via technology. This alternative approach achieves similar high-capacity stacking without the 30% cost burden and yield control difficulties associated with TSV.
3Ease of manufacture
If panel-level fan-out process is used to increase chips per substrate, then manufacturing cost is reduced, but warpage of 2-3 mm occurs creating 10 mm gap between substrate and chip
Solution Approach 1:
The patent applies preliminary action by pre-forming the electrical connection frame on the substrate before chip stacking and encapsulation. This pre-structured framework provides mechanical support that compensates for and controls warpage during panel-level processing, maintaining substrate-flatness while enabling cost-effective high-volume manufacturing.
4Reliability
If conventional slotting method is used to form conductive posts, then connection can be achieved, but higher slotting precision is required and excessive slotting occurs
Solution Approach 1:
The patent eliminates the need for post-stack slotting by pre-forming the electrical connection frame with conductive posts and distribution layers before chip stacking. This preliminary formation of connection structures removes the precision-critical slotting step entirely, reducing manufacturing complexity and eliminating excessive slotting issues.
Data Source
AI summary
The present disclosure provides a three-dimensional stacking fan-out packaging device and a method for preparing a three-dimensional stacking fan-out packaging device, and relates to the field of chip packaging. In this device, the concave chip bonding area is defined by the pre-supported electrical connection frame; a plurality of first chips with functional surfaces towards the first direction and a plurality of second chips with functional surfaces towards the second direction are arranged in the chip bonding area; and the first stacking chip and the second stacking chip are arranged in a central symmetry or plane symmetry.