Fan-Out Package Multi-Layer RDL Planarization
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Solution Overview
Problem
Conventional 2D and 3D wafer-level fan-out (WLFO) technologies face limitations in minimum line spacing and mechanical stress due to polyimide films, leading to non-planar RDL structures that restrict the number of interconnect layers and routing complexity in multi-chip modules.
Innovation Solution
The implementation of a redistribution layer (RDL) structure with planarized polymer layers over metallization layers, allowing for multiple interconnect layers and increased routing complexity by using milling to achieve a substantially planar surface for conductor traces, enabling more than three interconnect layers and reducing warpage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2D and 3D WLFO technologies use polyimide films for RDL structures, then the manufacturing process is simple, but the minimum line spacing is limited and the structure becomes non-planar
Solution Approach 1:
The patent changes the material parameter from polyimide film to planarized polymer layers with controlled topography, enabling sub-10 micrometer line spacing while maintaining manufacturing feasibility through standard planarization processes
Solution Approach 2:
The patent transitions from conventional 2D WLFO to 3D WLFO by stacking multiple RDL layers vertically, achieving complex routing patterns that cannot be realized in a single layer while maintaining planar surfaces for subsequent processing
2Ease of manufacture
If polyimide films are used in conventional WLFO, then the process is straightforward, but mechanical stress and warpage increase
Solution Approach 1:
The patent changes the mechanical properties of the polymer layers through planarization, reducing internal stress and improving dimensional stability while maintaining the ease of polymer-based fabrication
Solution Approach 2:
The patent applies planarization processes before subsequent RDL fabrication steps, preemptively eliminating topography-induced stress and warpage that would otherwise propagate through subsequent manufacturing steps
3Device complexity
If conventional RDL structures are used, then the structure is simple, but the number of interconnect layers is restricted to three or fewer
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple planarized RDL layers, enabling five or more interconnect layers and significantly increasing routing capacity compared to conventional 2D structures
Solution Approach 2:
The patent divides the RDL structure into multiple discrete planarized layers, each capable of independent routing, allowing complex signal distribution that cannot be achieved in fewer layers
Data Source
AI summary
Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.