Fan-out Semiconductor Package Integration
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in miniaturization, mounting precision, and reducing the number of processes while preventing bleeding defects of connection pads due to encapsulants, especially in fan-out packages with compact sizes and multiple pins.
Innovation Solution
A fan-out semiconductor package design that integrates first and second semiconductor chips without dicing, using a core member with redistribution layers and encapsulant to reduce process steps, improve precision, and minimize bleeding defects by spacing connection pads away from partition walls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are diced by a dicing processor before packaging, then individual chips can be handled and packaged separately, but the number of processes increases and mounting precision deteriorates
Solution Approach 1:
The patent applies preliminary action by keeping multiple semiconductor chips physically integrated on the wafer before packaging, rather than dicing them separately. The chips are packaged together in their integrated state, which reduces the number of handling steps and improves mounting precision while maintaining productivity through efficient use of the wafer structure.
2Adaptability or versatility
If multiple semiconductor chips are packaged separately, then each chip can be optimized individually, but the overall package size increases and process complexity increases
Solution Approach 1:
The patent merges multiple semiconductor chips by packaging them together in their physically integrated state on the wafer. This combining approach reduces process complexity by treating the integrated chips as a single packaging unit, while still allowing individual chip optimization through the redistribution layer design that can accommodate different chip types and configurations.
3Volume of moving object
If connection pads are placed close to partition walls for compact layout, then package size is reduced, but bleeding defects occur due to encapsulant intrusion
Solution Approach 1:
The patent introduces an intermediary structure (the redistribution layer and its associated patterning) that mediates between the connection pads and the encapsulant. This intermediary layer prevents direct contact between the encapsulant and connection pads, eliminating bleeding defects while maintaining compact package size through the fan-out redistribution design.
4Ease of operation
If chips are diced into smaller individual units, then handling and packaging flexibility improves, but the number of process steps increases and time consumption increases
Solution Approach 1:
The patent performs preliminary packaging on the integrated wafer structure before final separation, which reduces the number of subsequent handling steps. By packaging chips in their integrated state, the process eliminates multiple separate handling operations that would be required if chips were diced individually first, thereby reducing total process time while maintaining operational flexibility.
Data Source
AI summary
A fan-out semiconductor package includes: a first semiconductor chip having an active surface having first connection pads disposed thereon and an inactive surface opposing the active surface; a second semiconductor chip having an active surface having second connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of each of the first and second semiconductor chips; and a connection member disposed on the active surface of each of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second connection pads, wherein the first and second semiconductor chips are physically integrated with each other, and the first and second semiconductor chips have internal circuits, respectively.