Automatic Fault Detection in Inter-Power Domain Timing Analysis
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Solution Overview
Problem
Existing electronic circuit design methods lack efficient automatic fault detection and diagnostics in inter-power/voltage domain (IPD) based timing analysis, making it difficult to identify and address faults in complex digital circuits.
Innovation Solution
A computer-implemented method for automatic fault detection in electronic circuit design, which involves reading design and power intent information, identifying inter-power domain paths, filtering them using a graph-based approach to detect faulty paths, and generating a report depicting these faulty paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuit simulation is used for timing measurement, then measurement accuracy is improved, but analysis speed deteriorates
Solution Approach 1:
The patent replaces rigorous circuit simulation (mechanical/computational heavy approach) with static timing analysis using simplified timing models. This substitution maintains sufficient timing measurement accuracy while dramatically improving analysis speed, making the process practical for large-scale digital circuits.
Solution Approach 2:
The patent changes the modeling parameters from detailed circuit simulation models to simplified timing models that capture essential timing characteristics without the computational overhead of full simulation. This parameter simplification enables fast timing analysis while maintaining practical accuracy.
2Measurement precision
If manual fault detection is performed, then detection accuracy is improved, but time consumption increases
Solution Approach 1:
The patent implements automatic fault detection where the timing analysis system self-diagnoses and identifies faulty inter-power domain paths without requiring manual intervention. The system automatically extracts timing paths, analyzes power domain crossings, and generates fault reports, eliminating the need for manual inspection while maintaining high detection accuracy.
Solution Approach 2:
The patent incorporates feedback mechanisms where the timing analysis system continuously monitors timing paths and automatically identifies faults based on extracted information. The system feeds back timing path data, power domain transition information, and fault conditions to generate comprehensive fault reports, enabling automated detection and diagnosis.
3Reliability
If comprehensive timing analysis is performed, then analysis thoroughness is improved, but computational complexity increases
Solution Approach 1:
The patent segments the timing analysis process into distinct phases: extracting timing paths, identifying power domain crossings, analyzing fault conditions, and generating reports. This segmentation allows comprehensive analysis of IPD paths while managing computational complexity through structured processing and targeted analysis of critical paths.
Solution Approach 2:
The patent extracts only the essential information needed for fault detection from the comprehensive timing data. By extracting timing path information, power domain transition details, and fault conditions, the system achieves thorough analysis while reducing computational complexity through selective data processing and focused fault identification.
Data Source
AI summary
Embodiments include herein are directed towards a method for automatic detection during a timing analysis. Embodiments may include reading, using a processor, design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths from the design and power intent information. Embodiments may further include automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach and automatically generating a report depicting the one or more faulty inter-power domain paths.