Fault Injection Unit for Digital Circuit Simulation Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a lack of standard methods for injecting faults and analyzing fault tolerance mechanisms in digital circuit designs, particularly for Very Large Scale Integration (VLSI) processors, which hinders the evaluation of fault tolerance effectiveness at development time.
Innovation Solution
A method and apparatus that inject faults into a simulation of a digital circuit design using a Programming Language Interface (PLI) to extract design information, manipulate registers, and analyze the influence of faults on the simulation, enabling evaluation of fault tolerance mechanisms by comparing normal and fault-injected simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault injection and analysis methodology is implemented, then fault tolerance effectiveness can be evaluated, but no standard means exists for injecting faults and analyzing the effectiveness of implemented fault tolerance mechanisms
Solution Approach 1:
The patent introduces a fault injection unit as an intermediary component that interfaces between the test environment and the digital circuit design. This unit receives test input data, injects faults into the circuit simulation, and passes the faulted data through to the fault tolerance analysis unit, thereby enabling systematic evaluation of fault tolerance mechanisms without requiring complex direct manipulation of the circuit under test
Solution Approach 2:
The apparatus is segmented into distinct functional units: an information extraction unit that separates design information extraction, a fault injection unit that handles fault injection, and a fault tolerance analysis unit that performs analysis. This segmentation allows each unit to be optimized independently and facilitates modular implementation, reducing overall system complexity while enabling comprehensive fault tolerance evaluation
2Measurement precision
If faults are injected into simulation to analyze fault tolerance, then vulnerabilities can be identified, but the process requires comparing normal simulation with fault-injected simulation
Solution Approach 1:
The apparatus performs preliminary extraction of design information from the digital circuit design before fault injection occurs. The information extraction unit prepares the necessary design data structures and circuit model in advance, so that when faults are injected, the simulation can proceed efficiently with pre-configured parameters and comparison criteria already in place
Solution Approach 2:
The system creates a copy of the normal simulation output and compares it with the fault-injected simulation output. By maintaining parallel simulation traces (normal and faulted) and comparing their outputs, the system achieves precise fault detection without requiring re-simulation, thereby reducing the time loss associated with repeated simulations
Data Source
AI summary
Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.