FDC-PLL Bandwidth Calibration for Stable Gain Across Variations

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Solution Overview

Problem

Phase-locked loop (PLL) devices face challenges in maintaining consistent bandwidth due to varying analog gain over process and temperature variations, leading to jitter and settling time issues.

Innovation Solution

The implementation of foreground and background bandwidth calibration techniques, which include applying pulses to a frequency-to-phase accumulator to estimate and adjust calibration gain adjustments, ensuring the PLL's bandwidth remains consistent despite process and temperature variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If analog gain is used in the PLL device, then the bandwidth can be adjusted, but the bandwidth becomes inconsistent due to process and temperature variations

Engineering Contradiction:

Improvebandwidth adjustment capabilityVSAvoidbandwidth consistency

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the parameter from analog gain to digital gain calibration. By using digital calibration values applied to the digitally-controlled oscillator, the system maintains bandwidth adjustment capability while eliminating the inconsistency caused by analog gain variations due to process and temperature effects.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the analog gain control mechanism with a digital calibration mechanism. Instead of using analog components that are sensitive to environmental variations, the system uses digital calibration values stored in memory and applied through digital logic, thereby substituting an analog system with a digital one that is more stable and consistent.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If foreground calibration is performed, then initial bandwidth accuracy is improved, but the calibration process adds time during device initialization

Engineering Contradiction:

Improvebandwidth calibration accuracyVSAvoidinitialization time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs bandwidth calibration in advance during the manufacturing or initialization process and stores the calibration values in memory. This preliminary action ensures that the PLL starts with pre-calibrated digital gain values, achieving high bandwidth accuracy without requiring time-consuming calibration during normal operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a dynamic calibration system that can operate in different modes. The foreground calibration provides high accuracy when needed, while the system can switch to using stored calibration values during normal operation, thus balancing accuracy requirements with time constraints through dynamic mode switching.

Inventive Principle:

Principle #15Dynamics

3Reliability

If background calibration is implemented, then continuous bandwidth accuracy is maintained, but the device complexity increases

Engineering Contradiction:

Improvecontinuous bandwidth accuracyVSAvoidcalibration system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service calibration system where the PLL automatically performs background calibration using its own operational signals. The system monitors its own performance and adjusts digital calibration values without requiring external intervention or complex additional calibration equipment, thereby maintaining continuous accuracy while limiting complexity growth.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent designs the calibration system to serve multiple functions: it can perform foreground calibration during initialization, background calibration during operation, and store calibration values for later use. This multi-functionality allows a single calibration subsystem to handle various calibration needs, reducing overall device complexity compared to having separate systems for each calibration mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If digital calibration is applied, then immunity to environmental variations is improved, but the calibration precision requirements increase

Engineering Contradiction:

Improveimmunity to process and temperature variationsVSAvoidcalibration gain measurement precision

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms in the calibration process where the system measures the actual PLL performance and uses this feedback to refine the digital calibration values. By iteratively measuring and adjusting, the system achieves high precision calibration gain measurements despite the increased precision requirements, while maintaining immunity to environmental variations through the digital implementation.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9461657B2Foreground and background bandwidth calibration techniques for phase-locked loops

Publication Date: 2016.10.04 QUALCOMM INC

AI summary

Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.