FDSOI Transistor Defect Density Measurement via Capacitance Slope
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Solution Overview
Problem
Existing methods for assessing the electrical performance of FDSOI transistors over time are complex due to the need for intricate modeling of interface states, making it difficult to monitor changes in defect densities at dielectric/semiconductor interfaces, which affect the transistors' performance.
Innovation Solution
A method involving the measurement of capacitances in FDSOI transistors before and after an operating period, using specific voltage applications and calculations to determine variations in defect densities at the gate-channel and buried dielectric interfaces, without requiring complex modeling, allowing for the assessment of transistor deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex modeling of interface states is used to assess electrical performance, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential measurement function from the complex modeling process. By using capacitance measurements at specific voltages (VBG > 0 for NMOS, VBG < 0 for PMOS) and analyzing the slope of the C-V curve, the method obtains defect density information without requiring complex interface state modeling. The key insight is that the slope dC/dVBG at the inflection point directly relates to defect density through a simplified formula, eliminating the need for intricate models while maintaining measurement accuracy.
Solution Approach 2:
The patent changes the measurement parameter from direct defect density measurement (which requires complex modeling) to capacitance measurement (which is straightforward). By measuring capacitance C as a function of voltage VBG and analyzing the slope at the inflection point, the method transforms a complex parameter measurement into a simple electrical measurement. The relationship is given by: Dit = (2/εox) × (dC/dVBG)^-1, where εox is the oxide permittivity.
2Measurement precision
If complex modeling is used to describe electrical response, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent extracts the measurement procedure from the complex modeling framework. The method requires only standard capacitance measurement equipment and simple voltage application (VBG > 0 for NMOS, VBG < 0 for PMOS). The operator simply measures the capacitance slope at the inflection point and uses the formula Dit = (2/εox) × (dC/dVBG)^-1 to obtain defect density, without needing to perform complex modeling calculations or interpret complex electrical response characteristics.
3Measurement precision
If complex modeling is used to monitor changes over time, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent extracts a rapid measurement method that does not require complex modeling computations. The procedure involves: (1) applying voltage VBG > 0 (NMOS) or VBG < 0 (PMOS), (2) measuring capacitance C as a function of voltage, (3) identifying the inflection point and calculating the slope dC/dVBG, (4) computing defect density using the simple formula. This streamlined approach enables quick monitoring of defect density changes over time without the computational burden of complex modeling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the measurement process by focusing on capacitance variations to quantify changes in defect densities, enabling effective monitoring of transistor performance degradation over time with reduced computational complexity.
Implementation Method 1
measurement of the transistor's capacities C1 and C2 respectively in the first and second states, by applying a voltage VBG>0 to the substrate when the transistor is of the NMOS type, or a voltage VBGFG applied between a gate and source and drain areas of the transistor
Data Source
AI summary
A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps:measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas,determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1−1((Cmax+Cplat)/2) and VLower(0)=C1−1((Cmin+Cplat)/2),determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2−1((Cmax+Cplat)/2) and VLower(t1)=C2−1((Cmin+Cplat)/2),determination of variations of defect densities ΔDit1, ΔDit2 between the transistor's first and second states, at the transistor's front and back interfaces, from values ΔVUpper(t1)=VUpper(t1)−VUpper(0) and ΔVLower(t1)=VLower(t1)−Vlower(0).