FDSOI Transistor Back-Bias Control for High Current and Low Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current resistive memory technologies, particularly those using FDSOI-type substrates, face challenges in increasing passing current while limiting current leakages, leading to inhomogeneous performance and reduced programming window, which hinders the development of Multi-Level Cells (MLC) and memory cell density.
Innovation Solution
A transistor control device with transistors of a single conductivity type, utilizing a bias circuit to apply forward and reverse back-bias voltages, along with a second voltage-controllable well for dynamic isolation, allowing for extended threshold voltage modification and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of the selection transistor is reduced to increase memory cell density, then the memory cell density increases, but the passing current capability of the transistor decreases
Solution Approach 1:
The patent applies back-bias voltage to the substrate to dynamically modify the transistor's threshold voltage and electrical characteristics. By changing the substrate potential, the transistor can operate with enhanced current capability even at reduced dimensions, resolving the contradiction between small size and current capability.
2Power
If forward back-bias is applied to increase passing current, then the passing current increases, but current leakages increase
Solution Approach 1:
The patent employs dynamic back-bias control where the substrate voltage is adjusted according to the operational state. During write operations, forward back-bias enhances current capability, while during read or standby states, reverse back-bias suppresses leakage. This dynamic adaptation resolves the contradiction between passing current and leakage.
3Object-generated harmful factors
If reverse back-bias is applied to limit current leakages, then current leakages are reduced, but the passing current capability decreases
Solution Approach 1:
The system dynamically switches between reverse back-bias for leakage suppression and forward back-bias for current enhancement based on operational requirements. This temporal separation of functions allows the transistor to exhibit low leakage during standby and high current capability during active operations.
4Adaptability or versatility
If analogue voltage control circuits are added to enable MLC programming, then MLC capability is achieved, but the circuit complexity increases
Solution Approach 1:
The substrate back-bias control mechanism serves multiple functions: it enables MLC programming by providing fine-grained threshold voltage control, suppresses leakage, and enhances current capability. This multi-functionality achieves MLC capability without requiring separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the homogeneity of transistor performance, increases passing current, reduces memory cell size, and enables efficient MLC programming, thereby improving energy efficiency and memory cell density.
Implementation Method 1
A solution consists of applying a bias on the back face of the transistor (technique called BB for 'back-biasing'), which makes it possible to dynamically modulate the threshold voltage of the transistor and therefore its capacity to be provided to the current.
Implementation Method 2
An insulating layer based on a dielectric material on said substrate
Data Source
AI summary
An FDSOI transistor control device includes a plurality of first wells having a first type of conductivity, each first well being associated with a group of transistors, and at least one second well having a second type of conductivity, formed under and around the first wells (21). A bias circuit is configured to apply at least one first bias voltage to the first wells and at least one second bias voltage to at least one second well. All of the transistors may have the second type of conductivity.