FDSOI ESD Protection Diode With Shallow Isolation Trenches
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Solution Overview
Problem
Integrated circuits produced using FDSOI technology face challenges in generating transistors with distinct threshold voltages due to limited doping variations, leading to issues with electrical performance and reliability, particularly with leakage currents and fabrication control in ESD protection devices.
Innovation Solution
The use of isolation trenches of restricted depth and dimensions, along with a p-n junction diode structure, improves the structural and electrical properties of ESD protection devices by reducing leakage currents and enhancing control over electrical properties like breakdown voltage, allowing for the production of transistors with varying threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation trenches are made deep to separate ESD protection devices, then electrical insulation is improved, but manufacturing complexity and risk of damage increase
Solution Approach 1:
The patent applies local quality by creating isolation trenches with varying depths at different locations. Specifically, trenches are made deeper in regions where ESD protection devices are present compared to other areas of the circuit. This localized approach provides enhanced electrical insulation precisely where needed for ESD protection while avoiding the manufacturing complexity and damage risks associated with uniformly deep trenches across the entire substrate.
2Adaptability or versatility
If doping level of channel is varied to differentiate threshold voltages, then transistor performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration of the ground plane rather than varying the channel doping to achieve threshold voltage differentiation. By adjusting the doping level of the ground plane (e.g., from 10^16 to 10^18 atoms/cm³), the patent achieves the desired threshold voltage variations in transistors while avoiding the manufacturing precision challenges associated with controlling channel doping levels in FDSOI technology.
3Adaptability or versatility
If ESD protection devices are integrated alongside low-power logic gates, then circuit functionality is improved, but leakage currents increase
Solution Approach 1:
The patent applies the extraction principle by removing excess doping from the channel region of transistors used in low-power logic gates. Specifically, the channel doping is reduced to approximately 10^15 atoms/cm³, which eliminates parasitic triggering effects and reduces leakage currents. This allows ESD protection devices to be integrated alongside low-power logic gates without the harmful leakage effects that would otherwise occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance and reliability of ESD protection devices by minimizing leakage currents and improving control over electrical properties, enabling the production of transistors with distinct threshold voltages, thus improving the overall performance and efficiency of integrated circuits.
Implementation Method 1
A p-n diode, made on a side of the transistor and under the insulating layer
Implementation Method 2
This p-n diode comprises first and second semi-conducting zones, of opposite dopings, between which extends a third semi-conducting zone of lower doping level
Data Source
AI summary
An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.