FDSOI Transistors with Charged Dielectric Layers for Threshold Control

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Solution Overview

Problem

FDSOI technology faces challenges in forming transistors with voltage threshold control due to increased junction leakage between heavily doped back gates, which complicates the fabrication process and limits the back bias range.

Innovation Solution

The use of differently charged fixed charge dielectric layers beneath FDSOI transistors allows for independent threshold voltage control by employing silicon nitride and aluminum oxide layers with distinct fixed charges, enabling the formation of transistors with varying threshold voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If heavily doped back gates are used to maintain voltage threshold control, then voltage threshold control is improved, but junction leakage increases

Engineering Contradiction:
Improvevoltage threshold controlVSAvoidjunction leakage
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The invention changes the doping concentration parameter of the back gate, using lightly doped or undoped back gate compared to conventional heavily doped back gates. This parameter change reduces junction leakage while maintaining voltage threshold control through the fixed charge dielectric layer, directly resolving the contradiction between voltage threshold control and junction leakage.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention introduces a fixed charge dielectric layer as an intermediary between the back gate and the semiconductor film. This intermediary layer provides the necessary electric field for voltage threshold control without requiring heavy doping in the back gate, thus reducing junction leakage while maintaining control capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If shallow-trench-isolations are formed to prevent junction leakage, then junction leakage is reduced, but fabrication complexity increases

Engineering Contradiction:
Improvejunction leakageVSAvoidfabrication complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The invention extracts and removes the shallow-trench-isolation step from the fabrication process. By using lightly doped or undoped back gates combined with fixed charge dielectric layer, the patent eliminates the need for additional isolation structures, thereby reducing fabrication complexity while still preventing junction leakage.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If heavily doped back gates are used to maintain voltage threshold control, then voltage threshold control is improved, but back bias range is limited

Engineering Contradiction:
Improvevoltage threshold controlVSAvoidback bias range
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The invention changes the doping concentration parameter of the back gate to lightly doped or undoped, which expands the acceptable back bias range. This parameter change allows broader voltage operation while maintaining threshold control through the fixed charge dielectric layer, resolving the contradiction between control precision and adaptability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces junction leakage and enhances voltage threshold control, simplifying the fabrication process while maintaining reduced complexity and cost.

Implementation Method 1

The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages

Methodology Applied
Scientific EffectFixed charge: Electrostatics

Data Source

PatentUS10629620B2Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages
Publication Date: 2020.04.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10629620B2 patent drawing
  • US10629620B2 patent drawing

AI summary

According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.