FDSOI Back Bias Placing and Routing via Standard Tap Well Cells
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Solution Overview
Problem
Implementing back bias in fully depleted silicon-on-insulator (FDSOI) technology poses challenges due to incompatibility with existing design tools and requires additional routing steps, making it difficult to design complex integrated circuits without introducing complexity or design errors.
Innovation Solution
A placing and routing method involving standard tap well cells with p-BIAS and n-BIAS wires in one metallization layer and power/ground rails in another, where the bias wires extend across the rails, allowing continuous connection and simplifying the design process by adhering to high voltage design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If back bias is implemented in FDSOI technology using conventional approaches, then different threshold voltages can be achieved for different transistors, but the design process becomes complex and incompatible with existing CAD tools
Solution Approach 1:
The patent segments the back bias implementation into standardized tap well cells that can be independently placed and routed. Each tap well cell contains the necessary biasing structure for a single transistor, allowing complex circuits to be built from modular units that are easier to design and route.
Solution Approach 2:
The patent introduces tap well cells as intermediary structures between the power/ground rails and the transistor gates. These tap well cells serve as mediators that simplify the routing process by providing standardized connection points, eliminating the need for complex direct routing from power/ground to multiple transistor gates.
2Manufacturing precision
If additional routing steps are added to implement back bias, then threshold voltage control is improved, but the routing complexity and risk of design errors increase
Solution Approach 1:
The patent performs preliminary action by pre-configuring tap well cells with standardized biasing structures before the final routing is completed. The tap well cells are prepared in advance with proper connections to power and ground, so that during the routing process, only simple connections to transistor gates are needed, reducing the complexity of routing steps.
Solution Approach 2:
The patent changes the parameter approach from individual transistor-level biasing to cell-level standardized biasing. By using tap well cells with fixed biasing configurations, the design allows for threshold voltage control through cell placement and selection rather than complex individual routing for each transistor, simplifying the overall routing process.
3Productivity
If existing CAD tools are used for FDSOI design, then design efficiency is maintained, but the tools are incompatible with back bias implementation requirements
Solution Approach 1:
The patent makes the tap well cell design universal and compatible with existing CAD tools by using standardized cell structures and routing patterns. The tap well cells can be integrated into existing place-and-route flows without requiring specialized tools, allowing FDSOI designs with back bias to use the same CAD ecosystem as conventional FDSOI designs.
Data Source
AI summary
The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.