FDSOI Self-Aligned BULEX Edge for Well Tap Placement
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Solution Overview
Problem
Existing methods for forming fully depleted silicon-on-insulator (FDSOI) devices result in increased space between well contacts and active gates, leading to reduced chip density and efficiency due to the need for abundant back gates and well taps.
Innovation Solution
The method involves forming a self-aligned edge using a bulk-exposed layer (BULEX) to separate well taps from source/drain regions, minimizing the space between them and eliminating the need for trench isolation, thereby directly abutting the silicon oxide insulator to reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench isolation is used to separate well taps from source/drain regions, then isolation reliability is improved, but device area increases and chip density decreases
Solution Approach 1:
The patent extracts and removes the trench isolation structure entirely, replacing it with a self-aligned BULEX edge approach. The bulk exposed layer edge directly abuts the source/drain regions without requiring trenches, eliminating the isolation structure while maintaining electrical isolation through the self-aligned geometry and oxide layer positioning.
Solution Approach 2:
The BULEX edge serves multiple functions simultaneously: it provides the isolation boundary, defines the active area boundary, and enables self-alignment of the well tap to the source/drain regions. The structure is self-aligning through the etch stop layer geometry, eliminating the need for separate alignment processes and reducing area overhead.
2Reliability
If abundant back gates and well taps are placed in FDSOI devices, then device control and reliability are improved, but chip density decreases due to overhead loss
Solution Approach 1:
The patent merges the well tap formation with the active area definition process. The BULEX edge that defines the active area boundary simultaneously positions the well tap, combining two previously separate functions into a single self-aligned structure. This eliminates the need for separate alignment and reduces the overhead area required for well taps.
Solution Approach 2:
The BULEX edge structure serves multiple purposes: it defines the active area boundary, provides the isolation reference, enables self-alignment of well taps, and eliminates the need for trench isolation. This multi-functional approach reduces the number of separate structures needed, thereby increasing chip density while maintaining device control.
3Ease of manufacture
If well contacts are disposed at a distance away from active FDSOI gates, then manufacturing simplicity is improved, but active area efficiency decreases
Solution Approach 1:
The BULEX edge is formed in advance during the active area definition process, establishing the self-aligned reference before well tap formation. This preliminary action ensures that the well tap will be automatically positioned at the optimal location adjacent to the source/drain regions, maximizing active area efficiency while maintaining manufacturing simplicity through the self-aligned approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of back gates and well taps, increases active area efficiency, and minimizes the distance between well contacts and transistor diffusion regions, resulting in a more compact and efficient semiconductor device design.
Implementation Method 1
providing a silicon layer on a bulk oxide (BOX) layer on a silicon substrate
Implementation Method 2
forming a self-aligned edge using a bulk exposed layer (BULEX) edge to separate the well tap from source/drain regions
Data Source
AI summary
Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.