FE-FET XNOR Cell for Neuromorphic Computing
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Solution Overview
Problem
Existing neural networks face inefficiencies in performing multiply-accumulate operations, particularly in deep-learning neural networks, due to high computational intensity and noise associated with analog processing, and binary-weighted networks require more neurons to achieve comparable accuracy.
Innovation Solution
A digital XNOR computing cell utilizing ferroelectric field-effect transistors (FE-FETs) that performs binary or ternary XNOR operations, reducing noise and power consumption by storing weights locally and eliminating the need for analog processing, allowing for efficient and compact neuromorphic computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If binary-weighted networks are used to reduce power and noise, then power consumption and noise are reduced, but more neurons are required to achieve the same accuracy
Solution Approach 1:
The patent extends the weight representation from binary (2 levels) to ternary (3 levels: -1, 0, +1), effectively changing the parameter of weight quantization. This allows the network to represent more information per neuron, achieving comparable accuracy with fewer neurons while maintaining the low power consumption benefits of digital processing
Solution Approach 2:
The patent introduces a new dimension to the weight space by adding the zero weight category, transforming the weight representation from a 1-bit binary system to a 1.58-bit ternary system. This dimensional expansion enables more efficient information encoding without increasing the physical complexity of the neuron structure
2Power
If analog processing is used to perform MAC operations, then computational intensity is reduced, but noise and process variability increase
Solution Approach 1:
The patent replaces the mechanical/analog physical system with a digital electronic system. By implementing MAC operations using digital XNOR and count circuits, the invention eliminates the inherent noise and process variability of analog processing while maintaining computational efficiency through localized weight storage and digital logic operations
Solution Approach 2:
The patent segments the MAC operation into distinct digital stages: weight storage in FE-FETs, XNOR operation execution, and count circuit aggregation. This segmentation allows each function to be optimized independently and eliminates the need for continuous analog signal processing, thereby reducing noise accumulation
3Loss of energy
If weights are stored locally in each neuron, then power consumption and DRAM access frequency are reduced, but device complexity increases
Solution Approach 1:
The patent makes the FE-FET device perform multiple functions: it serves as both the weight storage element and the switching element for the XNOR operation. This multi-functionality eliminates the need for separate weight storage memory structures, thereby reducing device complexity while achieving local weight storage and reduced DRAM access frequency
Solution Approach 2:
The patent merges the weight storage function and the computational function into a single integrated structure. The weights are stored in the polarization state of the FE-FET, which is directly utilized in the XNOR operation, eliminating the need for separate weight registers or memory cells and simplifying the overall neuron architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The digital XNOR computing cell enhances the performance of neural networks by reducing noise, power consumption, and area requirements, enabling faster and more accurate operations with potentially fewer neurons, thus improving overall efficiency and accuracy.
Implementation Method 1
The pair(s) of FE-FETs include a ferroelectric layer that stores a weight
Data Source
AI summary
A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.