Feedback Clock Duty Cycle Matching in Clock Tracking Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock tracking circuits face issues with duty cycle mismatch between a reference clock and a feedback clock, leading to increased jitter and spurs, as separate corrections for duty cycle distortion in each clock signal can result in additive errors.
Innovation Solution
A clock tracking circuit with a duty cycle matching mechanism that adjusts the duty cycle of the feedback clock signal to match the reference clock signal, using a phase frequency detector, controller, and duty cycle matching circuit to generate a changed feedback clock with reduced mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate corrections for duty cycle distortion are applied to each clock signal, then individual duty cycle accuracy is improved, but additive errors increase causing greater overall mismatch
Solution Approach 1:
The patent merges the duty cycle correction operations into a single unified process. Instead of separately correcting duty cycle distortion in the reference clock and feedback clock, the system applies one correction operation to the feedback clock based on the duty cycle difference between the two clocks. This eliminates additive errors from multiple separate corrections while maintaining individual duty cycle accuracy.
2Measurement precision
If duty cycle matching correction is applied to reduce jitter and spurs, then clock tracking accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent introduces a duty cycle matching correction circuit as an intermediary component between the phase frequency detector and the feedback clock path. This circuit measures the duty cycle difference between reference and feedback clocks, then applies corrective delay adjustments to the feedback clock. The intermediary structure isolates the complexity of duty cycle measurement and correction from the main clock tracking path, reducing overall system complexity while improving accuracy.
3Reliability
If duty cycle matching is implemented to reduce spurs and jitter, then signal quality is improved, but processing time increases
Solution Approach 1:
The patent implements preliminary duty cycle matching correction by continuously measuring and correcting the duty cycle difference between reference and feedback clocks before the clocks are used for critical timing operations. The duty cycle matching circuit proactively adjusts the feedback clock duty cycle based on measured differences, preventing jitter and spur generation rather than correcting them after they occur. This preliminary action reduces the need for subsequent error correction and minimizes processing delays.
Data Source
AI summary
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.