Feedback Clock Duty-Cycle Matching for Low-Jitter PLL Tracking
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Solution Overview
Problem
Existing clock tracking circuits face issues with duty cycle mismatch between reference and feedback clocks, leading to increased jitter and spurs, as separate correction processes for duty-cycle distortion in each clock signal can result in additive errors.
Innovation Solution
A hybrid phase locked loop (PLL) circuit with a duty cycle matching mechanism that adjusts the feedback clock signal's duty cycle and pulse width to align with the reference clock, using a phase frequency detector, controller, and duty cycle matching circuit to reduce mismatch through calibration and waveform shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate correction processes are applied to duty-cycle distortion in each clock signal, then individual clock signals can be corrected, but additive errors occur leading to increased jitter and spurs
Solution Approach 1:
The patent merges the correction processes for reference clock and feedback clock into a unified duty cycle matching circuit. Instead of separately correcting each clock signal through independent processes that accumulate errors, the circuit simultaneously processes both clock signals together, using a single correction mechanism that prevents additive errors while maintaining clock signal quality
2Reliability
If duty cycle matching circuit is added to align feedback clock with reference clock, then jitter and spurs are reduced, but device complexity increases
Solution Approach 1:
The duty cycle matching circuit is designed to perform multiple functions: it corrects duty cycle distortion in both reference and feedback clocks simultaneously, adjusts pulse widths, and ensures proper alignment. This multi-functional approach reduces the need for separate correction circuits for each clock signal, thereby limiting the increase in device complexity while achieving jitter and spur reduction
Data Source
AI summary
A method may include: detecting, during respective feedback-clock cycles, a duty-cycle difference between a feedback clock and a reference clock based on error signals; and adjusting a duty-cycle shaping circuit to modify the feedback clock's pulse width by a fixed known amount in response to respective detected differences.