Feedback Clock Selection Circuit for Fast Phase Switching
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Solution Overview
Problem
Deep submicron integrated circuit manufacturing is susceptible to spatial and temporal process variations, leading to timing variations in clock signals, which traditional worst-case design methodologies attempt to address with area overhead, but a Better Than Worst Case (BTWC) design approach requires handling timing degradation for variation resilience.
Innovation Solution
A clock switch architecture that uses feedback arrangements between latches in different branches to switch between clock phases, allowing for dynamic clock switching and elastic pipelined execution by borrowing or stealing time, thereby making the design resilient to timing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single global clock is distributed and different phases are generated locally, then device complexity is reduced, but timing precision deteriorates due to process variations
Solution Approach 1:
The patent implements dynamic clock phase selection where the clock select circuit can switch between different clock phases (e.g., PH0, PH1, PH2, PH3) based on real-time operating conditions. This dynamic adaptation allows the system to compensate for timing variations caused by process, voltage, and temperature (PVT) changes, thereby maintaining timing precision without requiring a complex static multi-clock distribution network.
Solution Approach 2:
The system changes the clock phase parameter dynamically by selecting from multiple available phases with different skew characteristics. The clock select circuit responds to timing error signals and adjusts which clock phase is used, effectively changing the timing parameters to adapt to varying operating conditions and compensate for manufacturing variations.
2Manufacturing precision
If multiple clock phases are generated and switched between, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a clock select circuit as an intermediary component that manages the switching between multiple clock phases. This intermediary handles the complexity of phase selection and switching, isolating the rest of the digital logic from the complexity of multi-phase clock management while still benefiting from the timing precision improvements.
Solution Approach 2:
The system employs feedback mechanisms where timing error detection triggers clock phase switching decisions. The clock select circuit monitors timing conditions and dynamically switches between phases based on detected timing errors, creating a closed-loop system that automatically compensates for timing variations without requiring complex open-loop control architecture.
3Productivity
If timing guardbands are reduced for typical operating conditions, then productivity is improved, but reliability deteriorates due to timing degradation under varying conditions
Solution Approach 1:
The patent enables dynamic adaptation to varying operating conditions by switching between multiple clock phases with different timing characteristics. This allows the system to maintain reliable timing even when operating away from typical conditions, as the clock phase can be adjusted to compensate for PVT variations without requiring large static timing guardbands.
Solution Approach 2:
The system prepares for potential timing degradation by having multiple clock phases available in advance, each with different skew characteristics. When timing degradation is detected or anticipated, the system can switch to a pre-prepared clock phase that provides the necessary timing margin, effectively cushioning against timing reliability issues before they occur.
Data Source
AI summary
The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.