FeFET 2-Bit Memory Using Asymmetric Polarization Readout
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Solution Overview
Problem
Current memory technologies face challenges in efficiently storing and retrieving multiple data states in a single transistor, particularly in ferroelectric field-effect transistors (FeFETs), where maintaining asymmetric polarization states for 2-bit data storage is complex and requires precise voltage control to avoid bit disturbance during read operations.
Innovation Solution
A 2-bit ferroelectric field-effect transistor (FeFET) design with a ferroelectric layer between the gate and source-drain regions, utilizing asymmetric polarization states represented by dipoles, allows for independent programming and reading of bits by applying specific voltage combinations to maintain data integrity and minimize bit disturbance during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If asymmetric polarization states are used for 2-bit data storage in FeFET, then storage capacity is improved, but device complexity increases due to precise voltage control requirements
Solution Approach 1:
The patent segments the single FeFET device into four distinct polarization states (00, 01, 10, 11) by utilizing asymmetric dipole configurations at different ends of the ferroelectric layer. This segmentation allows 2-bit storage capacity while managing complexity through defined state transitions and read operations.
Solution Approach 2:
The patent employs parameter changes by applying specific voltage combinations (Vg, Vs/d) to transition between polarization states. The voltage parameters are carefully controlled to achieve desired bit states while minimizing disturbance to other bits, resolving the complexity through systematic parameter management.
2Ease of operation
If read voltage is applied to retrieve data, then data retrieval is enabled, but bit disturbance occurs during read operations
Solution Approach 1:
The patent uses partial action by applying read voltages that are sufficient to detect the polarization state but controlled to remain below the threshold that would cause unwanted state transitions. This allows data retrieval while minimizing bit disturbance through carefully calibrated voltage levels.
Solution Approach 2:
The patent implements feedback mechanisms where the read operation detects the current polarization state and uses this information to determine appropriate subsequent write operations. This feedback loop ensures accurate data retrieval while preventing unintended bit changes through state-aware control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable storage and retrieval of four possible 2-bit data states with reduced bit disturbance during read operations, enhancing the efficiency and accuracy of data storage in FeFETs by leveraging the bistable polarization states of the ferroelectric layer.
Implementation Method 1
a first set of dipoles at a first end of the ferroelectric layer has a first polarization; and a second set of dipoles at a second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization
Implementation Method 2
leveraging the bistable polarization states of the ferroelectric layer
Implementation Method 3
applying specific voltage combinations to maintain data integrity and minimize bit disturbance during operations
Data Source
AI summary
A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.