3D FeFET Layout for Capacitance Matching Without Drain Current Loss

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Solution Overview

Problem

In designing MFMIS-FETs, reducing the capacitance ratio between the MFM structure and the FET while maintaining device performance is challenging, as reducing MFM capacitance decreases drain currents, limiting performance.

Innovation Solution

Implementing a three-dimensional FET structure with an effective area greater than the footprint, and maintaining the effective area of the MFM structure nearly equal to the FET footprint, achieves a desired capacitance ratio, reducing charge trapping and write voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the capacitance ratio between MFM structure and FET is reduced, then device performance is improved, but drain currents decrease

Engineering Contradiction:

Improvedevice performanceVSAvoiddrain currents

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The patent implements a three-dimensional FET structure where the effective area exceeds the footprint by utilizing vertical stacking and multi-layer configurations. This dimensional transition allows the FET effective area to be increased without proportionally increasing the MFM structure area, thereby improving the capacitance ratio and device performance while maintaining adequate drain currents.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the effective area of FET is increased, then capacitance ratio is improved, but device footprint increases

Engineering Contradiction:

Improvecapacitance ratioVSAvoiddevice footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent achieves increased FET effective area by transitioning to three-dimensional structures including vertical fins, stacked channels, and multi-layer gate configurations. These approaches increase the functional area in the vertical dimension while maintaining a compact lateral footprint, thereby improving capacitance ratio without proportionally increasing overall device area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs nested configurations where multiple FET channels are stacked vertically or arranged in overlapping layers, allowing the effective area to be increased by nesting functional elements within a compact footprint. This nested arrangement enables higher capacitance ratios while maintaining space efficiency.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12136672B2FeFET of 3D structure for capacitance matching

Publication Date: 2024.11.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.