FeFET Gate Stack With High-κ Interfacial Layer for Endurance
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Solution Overview
Problem
Ferroelectric field-effect transistors (FeFETs) with crystalline silicon channels face endurance limitations due to interfacial layer breakdown, which restricts their cycling endurance to less than 10^12 cycles, whereas thicker ferroelectric oxides suffer from bulk charge-trapping and larger write voltages, and thinner oxides experience hot electron-induced hole damage and channel/oxide interface degradation.
Innovation Solution
Incorporating a high-κ interfacial layer of thermally grown silicon nitride (SiNx) with a 4.5 nm layer of zirconium-doped ferroelectric hafnium oxide (HfO2) on a silicon-on-insulator channel, enhancing the permittivity and reducing electric field stress, thereby improving the endurance of FeFETs beyond 10^12 cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thin ferroelectric oxide layer (less than 5 nm) is used, then the write voltage is reduced and device structure is simplified, but hot electron-induced hole damage and channel/oxide interface degradation occur, limiting endurance to 10^4 to 10^6 cycles
Solution Approach 1:
A 2 nm Al2O3 interfacial layer is introduced between the silicon channel and the ferroelectric HfO2 layer. This intermediary layer prevents direct interaction between hot electrons and the channel, reducing hot electron-induced hole damage and interface degradation, thereby enabling endurance exceeding 10^12 cycles while maintaining thin ferroelectric oxide thickness
Solution Approach 2:
The gate stack employs a composite structure combining Al2O3 interfacial layer with zirconium-doped HfO2 ferroelectric layer. This composite material approach leverages the benefits of both materials: Al2O3 provides excellent interface quality and hot electron blocking, while doped HfO2 delivers strong ferroelectric properties with reduced coercive field, achieving both low write voltage and high endurance
2Stability of the object's composition
If a thick ferroelectric oxide layer (greater than 5 nm to 6 nm) is used, then the ferroelectric effect is enhanced and retention is improved, but bulk charge-trapping and interfacial layer breakdown occur due to large coercive fields requiring larger write voltages, limiting endurance to 10^4 to 10^6 cycles
Solution Approach 1:
Zirconium doping of HfO2 is employed to modify the ferroelectric properties, reducing the coercive field from typical values to below 500 kV/cm. This parameter change enables the use of thinner ferroelectric layers (4.5 nm) that maintain sufficient ferroelectric effect and retention while avoiding bulk charge-trapping and interfacial breakdown issues associated with thicker layers
Solution Approach 2:
The Al2O3 interfacial layer serves as a protective intermediary that prevents direct damage to the ferroelectric layer from hot electrons and interface degradation mechanisms. This allows the ferroelectric HfO2 layer to operate at optimized thickness without suffering from interfacial breakdown, thereby achieving both enhanced ferroelectric effect and improved endurance
3Productivity
If crystalline silicon is used as the channel material, then high-performance memory is achieved, but formation of an interfacial layer is inevitable, leading to interfacial layer breakdown and limiting endurance to less than 10^12 cycles
Solution Approach 1:
A 2 nm Al2O3 interfacial layer is deliberately formed between the crystalline silicon channel and the ferroelectric HfO2 layer. This controlled intermediary layer prevents direct silicon-ferroelectric contact, eliminating the interfacial breakdown issue while maintaining compatibility with high-performance crystalline silicon channels, thereby achieving endurance exceeding 10^12 cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a memory window of ~1 V with ±2.5 V DC sweep and maintains high endurance and retention behavior, with voltage pulses of ±3 V at 250 ns, significantly improving the reliability and performance of FeFETs.
Implementation Method 1
a high-κ interfacial layer of thermally grown silicon nitride (SiNx) with a 4.5 nm layer of zirconium-doped ferroelectric hafnium oxide (HfO2) on a silicon-on-insulator channel, enhancing the permittivity and reducing electric field stress
Implementation Method 2
a layer of ferroelectric material disposed over the interfacial layer
Data Source
AI summary
A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.