FeFET Memory Cell With Lever Capacitor Voltage Control
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Solution Overview
Problem
Current memory cell technologies face challenges in efficiently writing and reading data without causing read disturb or increasing write voltage, particularly in ferroelectric field-effect transistor (FeFET) memory cells with a single ferroelectric capacitor connected to a gate, which can lead to non-linear capacitance and voltage distribution issues.
Innovation Solution
Incorporating a lever capacitor structure in addition to the ferroelectric capacitor, allowing for controlled voltage distribution during write and read operations, reducing write voltages and preventing read disturb by adjusting the capacitance ratios and voltages applied to the ferroelectric and lever capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ferroelectric capacitor is connected to the gate in FeFET memory cells, then the memory cell structure is simplified, but non-linear capacitance and voltage distribution issues occur leading to read disturb and increased write voltage requirements
Solution Approach 1:
The patent divides the single capacitor function into two separate capacitors: a ferroelectric capacitor for data storage and a lever capacitor for voltage control. This segmentation allows each capacitor to perform its specific function optimally, resolving the non-linear capacitance issues and preventing read disturb while maintaining simplified overall structure.
2Reliability
If higher write voltages are applied to overcome voltage distribution issues, then reliable writing is achieved, but energy consumption increases and device stress increases
Solution Approach 1:
The lever capacitor acts as an intermediary element between the control circuitry and the ferroelectric capacitor. It provides controlled voltage distribution during write operations, enabling reliable data writing at lower voltages by mediating the voltage stress and preventing direct high-voltage application that would increase energy consumption and device stress.
3Reliability
If the capacitance ratio between ferroelectric and lever capacitors is optimized, then voltage distribution is improved, but device complexity increases
Solution Approach 1:
The patent optimizes the capacitance ratio parameter between the ferroelectric capacitor and lever capacitor to achieve proper voltage distribution. By carefully selecting and adjusting this physical parameter during design, the system achieves improved voltage control and reliability without requiring complex dynamic adjustment mechanisms, thus maintaining relatively simple device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient writing and reading of memory cells with reduced voltage requirements and minimized read disturb, maintaining effective control over the field-effect transistor and reducing depolarization of the ferroelectric capacitor.
Implementation Method 1
each of the one or more memory cells may include a first capacitor structure, a second capacitor structure, and a field-effect transistor structure
Data Source
AI summary
A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.