FeFET Memory Cell Lever Capacitor for Low-Voltage Write and Read
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Solution Overview
Problem
Conventional memory cell architectures, such as standard 1T1C ferroelectric field-effect transistor (FeFET) memory cells, face challenges in efficient writing and reading operations due to high voltage requirements and potential read disturbs, especially in AND architectures, which can lead to reverse junction leakages and power consumption issues.
Innovation Solution
Incorporating a lever capacitor structure in addition to the ferroelectric capacitor within the memory cell, allowing for a more efficient voltage distribution during write and read operations, thereby reducing the need for high write voltages and minimizing read disturbs by adjusting the capacitance ratios between the ferroelectric capacitor, lever capacitor, and field-effect transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high write voltages are applied in conventional 1T1C FeFET memory cells, then writing operation can be performed, but power consumption increases and reliability decreases due to reverse junction leakages
Solution Approach 1:
The memory cell is segmented into multiple functional components: a ferroelectric capacitor for data storage, a lever capacitor for voltage control, and a field-effect transistor for switching. This segmentation allows the writing operation to be divided into controlled steps where the lever capacitor manages voltage distribution, enabling writing at reduced voltages and avoiding the need for high voltages that cause reverse junction leakages and high power consumption
Solution Approach 2:
The lever capacitor acts as an intermediary element between the control circuitry and the ferroelectric capacitor. It mediates the voltage application process by providing controlled voltage distribution to the ferroelectric capacitor through the field-effect transistor, enabling precise control of the writing operation at reduced voltages and preventing harmful reverse junction leakages
2Ease of manufacture
If high write voltages are applied in conventional 1T1C FeFET memory cells, then writing operation can be performed, but reverse junction leakages occur reducing reliability
Solution Approach 1:
The memory cell is segmented into multiple functional components: a ferroelectric capacitor for data storage, a lever capacitor for voltage control, and a field-effect transistor for switching. This segmentation allows the writing operation to be divided into controlled steps where the lever capacitor manages voltage distribution, enabling writing at reduced voltages and avoiding the need for high voltages that cause reverse junction leakages and high power consumption
Solution Approach 2:
The lever capacitor acts as an intermediary element between the control circuitry and the ferroelectric capacitor. It mediates the voltage application process by providing controlled voltage distribution to the ferroelectric capacitor through the field-effect transistor, enabling precise control of the writing operation at reduced voltages and preventing harmful reverse junction leakages
3Ease of operation
If conventional reading operations are performed, then data can be read, but read disturbs occur affecting neighboring memory cells
Solution Approach 1:
The lever capacitor serves as a mediator during read operations, providing controlled voltage distribution that isolates the read operation to the selected memory cell. By adjusting the capacitance ratio between the lever capacitor and ferroelectric capacitor, the voltage applied during reading is precisely controlled, preventing voltage spikes that would cause read disturbs in neighboring cells while still enabling sufficient voltage for reliable data detection
4Ease of manufacture
If high voltages are applied during writing, then ferroelectric capacitor can be programmed, but depolarization occurs reducing data retention
Solution Approach 1:
The lever capacitor mediates the voltage application to the ferroelectric capacitor during programming, providing controlled voltage distribution that prevents excessive voltage spikes. By adjusting the capacitance ratio between the lever capacitor and ferroelectric capacitor, the voltage applied during programming is optimized to achieve reliable polarization switching without exceeding the threshold that would cause depolarization and data loss
Solution Approach 2:
The invention changes the voltage distribution parameters by introducing the lever capacitor with a specific capacitance ratio relative to the ferroelectric capacitor. This parameter change enables programming at reduced voltages and provides controlled voltage distribution during programming, preventing excessive voltage that would cause depolarization while still achieving reliable polarization switching for data storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced write voltages, prevents destructive read operations, and minimizes depolarization of the ferroelectric capacitor, while maintaining effective control over the field-effect transistor, thus enhancing the overall performance and reliability of memory cell operations.
Implementation Method 1
a first capacitive memory structure (104) coupled to a gate of the field-effect transistor structure (102) via a first control node (104c) of the memory cell (100); a second capacitive lever structure (106) coupled to the gate of the field-effect transistor structure (102) via a second control node (106c) of the memory cell (100)
Data Source
AI summary
A memory cell may comprise a field-effect transistor structure comprising a gate structure, the gate structure comprising a floating gate electrode separated from a channel of field-effect transistor structure by a gate isolation; a spontaneously polarizable memory layer, wherein the spontaneously polarizable memory layer covers completely an upper surface of the floating gate electrode and wherein the spontaneously polarizable memory layer covers one or more lateral surfaces of the floating gate electrode; a gate electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the gate electrode to form a capacitive memory structure; and a lever electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the lever electrode to form a lever structure.