FEOL Layer Thickness Balancing for Reduced Wafer Bow
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Solution Overview
Problem
Semiconductor wafer bow and warpage during processing lead to alignment issues and inconsistent IC performance, reducing yield and increasing costs due to localized damage and inconsistent feature formation.
Innovation Solution
A method involving the concurrent formation of front end of line (FEOL) layers with specific thicknesses on both the frontside and backside of a semiconductor substrate, followed by reducing the thickness of the backside layers to mitigate wafer bow and warpage, thereby improving alignment precision and reducing the tensile effect on the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FEOL layers are formed on both frontside and backside of the semiconductor substrate, then alignment precision is improved, but wafer bow and warpage increase due to tensile effects
Solution Approach 1:
The patent applies asymmetry by forming FEOL layers on both frontside and backside of the substrate but with different thicknesses. The backside layer thickness is specifically controlled to be less than the frontside layer thickness, creating an asymmetric structure that compensates for tensile effects and reduces wafer bow and warpage while maintaining alignment precision.
Solution Approach 2:
The patent changes the thickness parameter of the backside FEOL layer to optimize wafer flatness. By controlling the backside layer thickness to be less than the frontside layer thickness, the patent adjusts the mechanical parameters of the wafer structure to minimize tensile effects and reduce bow and warpage during processing.
2Shape
If backside layer thickness is reduced to minimize tensile effects, then wafer bow and warpage are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the backside FEOL layer with controlled thickness before completing the frontside processing. This preliminary thickness control prevents excessive tensile effects and wafer bow during subsequent processing steps, avoiding the need for complex corrective measures later in the manufacturing process.
Data Source
AI summary
Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.