FeRAM Select Gate Reduces Leakage Current
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Solution Overview
Problem
Ferroelectric random-access memory (FeRAM) devices experience unwanted currents in unselected 1T cells, leading to increased power consumption and negatively impacting read operations, especially as the size of these cells decreases.
Innovation Solution
Incorporating a select gate configured to selectively provide access to the FeRAM device, effectively operating as a 1.5 transistor FeRAM cell, which reduces current in channel regions of unselected cells and improves power consumption and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 1T FeRAM cell structure is used, then device complexity is reduced, but unwanted currents increase leading to higher power consumption
Solution Approach 1:
The FeRAM cell is segmented into two functional parts: a select transistor that controls access to the cell, and a storage element (ferroelectric capacitor) that holds the data. This segmentation allows the select transistor to block unwanted currents in unselected cells while the storage element maintains data, thereby reducing power consumption without significantly increasing overall device complexity.
Solution Approach 2:
A select transistor is introduced as an intermediary component between the bit line and the FeRAM storage element. This select transistor acts as a gatekeeper that controls current flow into the storage element, preventing leakage currents in unselected cells while allowing controlled access during read/write operations, thus reducing power consumption.
2Area of moving object
If cell size is decreased, then storage density increases, but unwanted currents negatively impact read operations
Solution Approach 1:
By segmenting the FeRAM cell into a select transistor and storage element, the patent enables better control over current paths. The select transistor can be optimized independently to provide sufficient switching strength even in scaled-down cells, while the storage element maintains data integrity. This segmentation allows read operations to proceed reliably despite reduced cell dimensions.
Solution Approach 2:
The select transistor serves as an intermediary that isolates the storage element from direct bit line connections when not selected. This isolation prevents unwanted currents from interfering with the delicate charge states in scaled-down storage elements, thereby maintaining read operation reliability even as cell size decreases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a select gate in FeRAM cells reduces power consumption and enhances read operations by minimizing current flow in unselected cells, particularly in smaller cell sizes.
Implementation Method 1
The FeRAM device includes a ferroelectric material arranged between a substrate and a conductive electrode
Data Source
AI summary
The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.