Ferroelectric 2D Material Gate Dielectric for CMOS Scaling
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, the reduction in minimum feature sizes introduces challenges that existing technologies have not adequately addressed, particularly in achieving improved gate dielectric layers for enhanced performance.
Innovation Solution
The formation of gate dielectric layers using ferroelectric two-dimensional materials with negative capacitance, matched to the positive capacitance of the substrate, to increase the on-off current ratio and gate voltage, is implemented in both planar MOSFETs and FinFETs, utilizing a gate-last process and including interfacial layers for fine-tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise that existing technologies cannot adequately address
Solution Approach 1:
The patent changes the physical parameters of the gate dielectric layer by using ferroelectric materials with negative capacitance properties. This fundamentally alters the electrical characteristics of the gate stack, enabling enhanced device performance at scaled dimensions through the negative capacitance effect that amplifies the gate voltage swing.
Solution Approach 2:
The patent employs composite material structures including ferroelectric 2D materials (such as indium selenide, tin telluride, or germanium sulfide) combined with conventional dielectric layers. This composite approach integrates the beneficial properties of ferroelectric materials into existing semiconductor fabrication processes, achieving improved performance while maintaining compatibility with standard manufacturing techniques.
2Reliability
If conventional gate dielectric layers are used in scaled devices, then manufacturing processes remain simple, but device performance and on-off current ratio are insufficient
Solution Approach 1:
The patent introduces interfacial layers as intermediary structures between the ferroelectric 2D material and the semiconductor channel. These interfacial layers serve as mediators that ensure proper electrical contact, manage interface states, and enable the ferroelectric material to function effectively while maintaining compatibility with the underlying semiconductor structure.
Solution Approach 2:
The patent modifies the gate dielectric parameters by implementing multi-layer structures with specific thicknesses and material compositions. The ferroelectric layer thickness, interfacial layer composition, and overall stack design are optimized to achieve the desired negative capacitance effect and improved device performance metrics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance of semiconductor devices by increasing the on-off current ratio and gate voltage, effectively addressing the integration density challenges and performance requirements in advanced CMOS technology.
Implementation Method 1
The gate dielectric layers may be formed of materials having a negative capacitance, such as ferroelectric two-dimensional (2D) materials
Data Source
AI summary
A semiconductor device including a 2D material layer disposed between a gate electrode and a substrate and a method of forming the same are disclosed. In an embodiment, a device includes a ferroelectric dielectric layer disposed over and in contact with a semiconductor substrate, the ferroelectric dielectric layer including a 2D material; a gate electrode disposed over the ferroelectric dielectric layer; and source/drain regions disposed on opposite sides of the gate electrode.