Ferroelectric Layer Capping Oxide for Memory Reliability
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Solution Overview
Problem
Current semiconductor devices with ferroelectric layers face challenges in achieving stable and reliable three-dimensional memory cell structures, particularly in maintaining polarized states of electric dipoles for nonvolatile memory applications, which affects their operational reliability and data storage capabilities.
Innovation Solution
A semiconductor device with a stack structure featuring a ferroelectric insulation layer and a channel layer sequentially stacked on a trench sidewall, where a capping oxide pattern with a different lattice constant and higher oxygen vacancy concentration than the ferroelectric insulation layer is used to enhance the ferroelectric property by inducing a crystalline structure and maintaining polarized states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a ferroelectric layer is used in three-dimensional memory cell structures, then nonvolatile data storage capability is achieved, but operational reliability deteriorates due to inability to maintain stable polarized states
Solution Approach 1:
A capping oxide layer is introduced as an intermediary between the ferroelectric layer and the environment. This capping oxide layer has a different lattice constant and higher oxygen vacancy concentration than the ferroelectric layer, which helps maintain the polarized states of electric dipoles in the ferroelectric layer, thereby improving operational reliability while preserving data storage capability
Solution Approach 2:
The patent changes the physical and chemical parameters of the capping oxide layer, specifically its lattice constant and oxygen vacancy concentration, to optimize its interaction with the ferroelectric layer. By controlling these parameters, the capping oxide layer can effectively maintain the polarized states in the ferroelectric layer, resolving the reliability issue
2Stability of the object's composition
If the lattice constant of the capping oxide layer matches the ferroelectric insulation layer, then structural compatibility is improved, but ferroelectric property enhancement is reduced
Solution Approach 1:
The patent deliberately changes the lattice constant parameter of the capping oxide layer to be different from that of the ferroelectric insulation layer. This parameter difference creates a controlled mismatch that generates strain in the ferroelectric layer, which enhances the ferroelectric property by stabilizing the polarized states, while still maintaining sufficient structural compatibility for device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the operational reliability of the semiconductor device by maintaining polarized states and enhancing the ferroelectric property of the ferroelectric insulation layer, enabling efficient data storage and independent control of channel resistance values for multiple data storage.
Implementation Method 1
annealing the ferroelectric material to form a ferroelectric insulation layer having a crystalline structure
Implementation Method 2
maintaining polarized states of electric dipoles for nonvolatile memory applications
Data Source
AI summary
A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material.