Ferroelectric Control Gate Reduces RC Delay in NAND Memory

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Solution Overview

Problem

High RC delay in word lines/control gate electrodes limits the speed of operation in charge storage memory devices like NAND memory devices.

Innovation Solution

Incorporating a ferroelectric layer between the control gate electrode layers to reduce RC delay and increase operational speed by utilizing a layer stack including a metallic barrier layer, a ferroelectric material layer, and a metallic fill material layer, which provides negative capacitance and improves sub-threshold slope and current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional control gate electrode layers are used in charge storage memory devices, then the device structure is simple and manufacturing is easier, but high RC delay limits the speed of operation

Engineering Contradiction:

Improveoperational speedVSAvoidcontrol gate electrode structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The control gate electrode is constructed as a composite structure comprising a first electrically conductive layer, a ferroelectric material layer, and a second electrically conductive layer. This composite structure reduces RC delay and enhances operational speed while maintaining manufacturability through sequential deposition processes.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The ferroelectric material layer acts as an intermediary between the two electrically conductive layers, providing negative capacitance that amplifies the voltage signal and reduces the overall RC delay of the control gate electrode, thereby improving switching speed without requiring changes to the underlying memory structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If a ferroelectric layer is added between control gate electrode layers, then RC delay is reduced and operational speed is enhanced, but the device structure becomes more complex

Engineering Contradiction:

ImproveRC delayVSAvoidlayer stack structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The ferroelectric material layer changes the electrical parameters of the control gate electrode by introducing negative capacitance, which effectively reduces the RC time constant. This parameter change enables faster switching speeds without requiring dimensional changes to the overall device structure.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The control gate electrode is segmented into three distinct functional layers: a first electrically conductive layer for charge storage, a ferroelectric material layer for negative capacitance effect, and a second electrically conductive layer for signal application. This segmentation allows each layer to be optimized independently while working together to reduce RC delay.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ferroelectric layer reduces RC delay, enhances operational speed, and improves read noise and program/erase efficiency in NAND memory devices.

Implementation Method 1

Methodology Applied

Scientific EffectNegative capacitance: Capacitance

Data Source

PatentUS11107901B2Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same

Publication Date: 2021.08.31 SANDISK TECHNOLOGIES LLC

AI summary

A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer.