Solid-State Devices TRIZ Cases

Segmented opposite electrode structure with auxiliary electrodes reduces resistance gaps in organic light-emitting displays.

A light-absorbing layer absorbs cyan wavelengths to enable specific color emission from subpixels without patterning individual color filters.

Relocates reflective metal layers to side walls in light emitting devices, preventing etching damage and reducing light loss.

A single-side light-emitting source uses segmented electrodes and light-shielding patterns to direct illumination toward the display panel.

Oxidizing conductive layers within contact holes to form variable resistance layers for non-volatile memory devices.

Selective etching removes polysilicon particles from control and select gates, resolving CMP-induced isolation degradation in integrated semiconductor devices.

A ferroelectric layer between conductive control gate electrodes provides negative capacitance to reduce electrical resistance-capacitance delay.

A resin package recess positions a light reflecting member to direct emitted light, preventing reflector expansion from heat accumulation.

Differentiated fixed charge films suppress dark current while preventing film peeling on etched grooves.

Nested capacitor electrodes reduce pixel area and current load by compensating for manufacturing precision deviations without expanding the display footprint.

A light shielding section embedded in the semiconductor substrate blocks oblique light paths between the photoelectric conversion element and the charge retaining section.

Composite protective patterns shield gate electrodes from etchant damage while reducing vertical width to eliminate voids and seams.

Segmented gate electrodes with lateral projections reduce I-V humps and power consumption in liquid crystal display peripheral circuits.

Ion implantation creates latch-up inhibiting regions in the substrate, increasing holding current and reducing resistances without requiring double guard rings.

A ring pattern layer guides upper and lower hole alignment in 3D memory stacks, suppressing process defects during deep etching.

Segmented substrate regions enable joint loading of memory cells with different gate lengths, resolving adaptability versus complexity trade-offs.

Optical gratings guide and extract fingerprint light rays, eliminating bulky lenses and pinhole filters to reduce device thickness.

Segmented ion implantation forms connected n-type regions in vertical gate NAND bit line pads, overcoming stacked layer masking during sidewall doping.

Segmented charge trap patterns with local insulating regions suppress cell interference in vertical memory devices, maintaining reliability at high densities.

A staircase-shaped protrusion in the insulating layer structure distributes polishing stress during semiconductor planarization.

Varying impurity density in a silicon film prevents constriction during anisotropic etching, ensuring vertical sidewalls for semiconductor devices.

Simultaneous laser decomposition and chemical etching prevents layer breakage, achieving mirror-quality surfaces without mechanical polishing.

An AlNiX alloy reflective film boosts blue light extraction while maintaining low sheet resistance.

A vertical thin film transistor structure increases photosensitive device area in fingerprint identification sensors.

A foldable display panel integrates pressure-sensitive devices within its bending region to detect mechanical deformation and determine the current bending angle.

Multiplexed light shading layers form a collimating structure that screens stray light, resolving blurriness in ultra-thin displays.

Screen printed silicone resin layer eliminates color irregularities by maintaining uniform film thickness over light emitting elements.

Automated voltage correction compensates for actuator variations, eliminating manual calibration time and ensuring uniform droplet volume.

Inverting subpixel arrangements in non-display regions compensates for optical distortions caused by bending, maintaining display quality consistency.

Cooling at less than 3.0°C/min prevents warpage mismatch that causes scratches and film thickness abnormalities.

A polymer structure with aryl and heteroaryl groups enhances power conversion efficiency in organic photovoltaic devices.

Memcapacitor cross-point memory cells use AC voltage to alter capacitance states, eliminating charge dissipation and refreshing needs.

A continuous metal source plate shields memory cells from voltage fluctuations on bit lines.

A semiconductor device uses a dedicated reference cell coupled to a constant-voltage source bit line to enable efficient charge accumulation and output.

A polymer material layer fills openings in a light shielding layer, creating protruding air vents that guide gas escape during adhesive bonding.

A nonplanarized adhesive film prevents color filter detachment while maintaining overlay accuracy and sensitivity.

A shielding layer absorbs or reflects incident laser light to prevent damage to circuit control boards during sapphire substrate removal.

A process control procedure monitors instantaneous deformation values during bonding to constrain geometric parameters within acceptable tolerances.

Alternately stacked gate electrodes and sacrificial layers form vertical channels, enabling enhancement-mode operation for higher integration density.

A flip-chip side emitting LED uses a phosphor window layer to direct light parallel to the active surface for thin backlighting.

Replacing lithium with zinc or bismuth dopants in the hole conductor layer reduces hygroscopicity while maintaining charge carrier transport efficiency.

A shallow trench isolation structure with an air gap prevents photon interference and dark current, ensuring uniform doping profiles.

Embedding sensors in substrate recesses reduces parasitic capacitance by shortening interconnections while protecting elements from physical damage.

A light sensing device uses a filter element with a distinct width relative to adjacent shielding and dielectric structures.

A protection layer shields connection portions during via-hole etching to maintain flat surfaces and electrical contact.

A programmable device architecture separates power routes for core logic and configuration memory to enable independent power control.

A sintering method defines closed patterns with arcuate sections to seal display substrates along non-rectilinear paths.

Three successive light-emitting sub-layers with tailored matrix materials confine excitons to reduce non-radiative transitions and improve current efficiency.