3D Nonvolatile Memory Pillar Asymmetric Width Area Reduction
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Solution Overview
Problem
Conventional 3D nonvolatile memory devices face a challenge in reducing the horizontal area without degrading their operation characteristics, as the vertical stacking of memory cells leads to increased horizontal width and area, limiting integration density.
Innovation Solution
The proposed nonvolatile memory device design includes vertically extending pillars and coupling portions with alternately stacked gate electrode and interlayer dielectric layers, where the uppermost gate electrode layer serves as a selection transistor gate, and the others as memory cell gates, with shared gate electrode layers between channels to reduce horizontal area by omitting trenches between adjacent channel holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical height of the nonvolatile memory device is increased to increase integration degree, then the number of vertically stacked memory cells increases, but the horizontal width of the uppermost parts of channel holes or trenches inevitably increases, causing the horizontal area to increase
Solution Approach 1:
The patent applies asymmetry by making the channel holes have different widths at different heights. Specifically, the channel holes are designed to be narrower at the uppermost parts and wider at lower parts, which is the opposite of conventional designs where uniform width is maintained. This asymmetric width distribution allows the device to achieve higher integration density without proportionally increasing the horizontal area occupied by the uppermost structures.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical stacking architecture. By stacking multiple memory cells vertically and using pipe channel holes that extend through multiple interlayer dielectric layers, the device achieves higher integration density in the vertical dimension while carefully controlling the horizontal footprint through the asymmetric channel hole design.
2Reliability
If trenches are formed between all channel holes to isolate gate electrode layers, then proper isolation is achieved, but the horizontal area and device complexity increase
Solution Approach 1:
The patent merges the isolation function across adjacent channel holes by forming a single continuous trench structure that serves multiple channels simultaneously. Instead of forming separate trenches between each pair of adjacent channel holes, the design uses shared trenches that provide isolation for multiple gate electrode layers, thereby reducing the total number of trenches and the associated horizontal area while maintaining proper electrical isolation.
3Manufacturing precision
If the horizontal width of uppermost channel holes is increased to compensate for etching characteristics, then etching uniformity improves, but the horizontal area of the device inevitably increases
Solution Approach 1:
The patent uses asymmetric channel hole geometry where the width varies with height. The channel holes are designed to be narrower at the uppermost parts and wider at lower parts. This asymmetric design compensates for etching characteristics that typically cause wider openings at the top, while keeping the horizontal area occupied by uppermost structures minimal, thus resolving the contradiction between etching uniformity and area reduction.
Data Source
AI summary
A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.