Trapping Gate Forming Process for Flash Memory

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Solution Overview

Problem

Flash memory devices experience lateral charge migration and threshold voltage loss due to the placement of trapping gates outside isolated areas, leading to inefficiencies in data retention and voltage stability.

Innovation Solution

A trapping gate forming process that involves forming an oxide/nitride/oxide layer on a substrate, patterning it to create an active area and trench, and then forming an isolation structure within the trench, ensuring the oxide/nitride/oxide layer is only in the overlapping area between the gate and active area, thereby reducing charge migration and threshold voltage loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the oxide/nitride/oxide layer is formed extensively on the substrate, then the trapping gate can be formed, but lateral charge migration and threshold voltage loss occur

Engineering Contradiction:
Improvedata retentionVSAvoidlateral charge migration
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The oxide/nitride/oxide layer is segmented into discrete regions corresponding to active areas, separated by isolation structures in trenches. This segmentation confines the trapping gate function to specific locations, preventing lateral charge migration while maintaining data retention capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The oxide/nitride/oxide layer is selectively formed only in active areas where trapping gates are needed, with different regions having different properties (active vs. isolated). This local quality approach ensures trapping gates are present where required while eliminating harmful charge migration in isolated regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If the oxide/nitride/oxide layer is trimmed precisely with isolation structure, then charge migration is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidpatterning process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patterning of the oxide/nitride/oxide layer and the formation of isolation structures are merged into a single integrated process. The same patterning steps that define active areas also create trenches for isolation structures, eliminating the need for separate trimming operations and reducing manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The isolation structure serves multiple functions: it physically separates active areas, defines the boundary of the oxide/nitride/oxide layer, and prevents charge migration. This multi-functionality reduces the need for additional dedicated structures or processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If the trench for isolation structure is defined by patterning the oxide/nitride/oxide layer, then alignment accuracy is improved, but process steps increase

Engineering Contradiction:
Improvealignment accuracyVSAvoidfabrication throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The oxide/nitride/oxide layer is formed and patterned in advance to define the locations where trenches will subsequently be formed. This preliminary action establishes precise alignment references before the isolation structure formation, ensuring accurate positioning without requiring additional alignment steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The process transitions from two-dimensional layer formation to three-dimensional structure creation by forming trenches perpendicular to the substrate surface. This dimensional change allows the isolation structure to vertically separate active areas while the horizontal patterning maintains alignment precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10096611B2Trapping gate forming process and flash cell
Publication Date: 2018.10.09 UNITED MICROELECTRONICS CORP
  • US10096611B2 patent drawing
  • US10096611B2 patent drawing
  • US10096611B2 patent drawing

AI summary

A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.