Semiconductor Device Reference Cell Arrangement for Read Time Reduction
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Solution Overview
Problem
Conventional DRAMs face increased read time due to reduced electric potential difference between the drain and source of memory cell transistors when using a half voltage for pre-charging, necessitating innovative arrangements of reference cells to enhance data detection efficiency without increasing semiconductor device area.
Innovation Solution
The semiconductor device incorporates a configuration with multiple bit lines and reference cells, where capacitances are coupled to bit lines and a constant-voltage source, allowing for efficient accumulation and output of electric charges, enabling improved arranging efficiency of reference cells and reduced read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a half voltage (1/2Vcc) is used for pre-charging the bit line to reduce power consumption, then power consumption is reduced, but the electric potential difference between drain and source of the memory cell transistor is reduced, causing increased read time
Solution Approach 1:
The invention divides the bit line system into two separate bit lines: one for memory cell access and another dedicated to reference cell pre-charging. This segmentation allows independent voltage control, enabling the reference bit line to be pre-charged to a higher voltage level while the memory bit line uses lower pre-charging voltage, thus resolving the contradiction between power consumption and read time
Solution Approach 2:
The invention introduces a reference cell as an intermediary element that is coupled to a dedicated reference bit line. This reference cell serves as a mediator to provide a stable reference potential, allowing the sense amplifier to accurately detect memory cell states even when using reduced pre-charging voltages, thereby maintaining fast read times while reducing power consumption
2Loss of time
If reference cells are added to enable ground pre-charging DRAM operation to increase electric potential difference and reduce read time, then read time is reduced, but the area of the semiconductor device increases
Solution Approach 1:
The invention merges the reference cell structure with the memory cell structure, using identical transistor and capacitor configurations for both. This allows the reference cell to be implemented using the same fabrication processes and occupying similar area as memory cells, minimizing the additional area overhead while enabling ground pre-charging operation that reduces read time
Solution Approach 2:
The reference cell is designed with the same multi-functional capability as memory cells, serving both as a reference for the sense amplifier and as a functional unit that can be integrated into the existing memory array layout. This universal design allows efficient space utilization, reducing the area penalty associated with adding reference cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient data readout from memory cells by utilizing ground pre-charging voltage, reducing read time and maintaining a compact semiconductor device layout.
Implementation Method 1
a first capacitance having electrodes, one of the electrode being coupled to the other of the source and the drain of the first transistor, which is not coupled to the first bit line
Implementation Method 2
a first transistor having a source and a drain, one of the source and the drain being coupled to the first bit line
Data Source
AI summary
A semiconductor device includes: a first sense amplifier; a first bit line coupled to the first sense amplifier; a second bit line disposed next to the first bit line and electrically coupled to a constant-voltage source; and a first reference cell, including: a first transistor having a source and a drain, one of which is coupled to the first bit line; a second transistor, having a source and a drain, one of which is coupled to the second bit line, and the other coupled to the other of the source and drain of the first transistor, which is not coupled to the bit line BL1a; and a capacitance C1 having electrodes, one of which is coupled to the other of the source and the drain of the first transistor, and the other of the source and the drain of Tr2.