Vertical Cell Semiconductor Gate Electrode Protective Patterns
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Solution Overview
Problem
In the fabrication of vertical cell-type semiconductor devices, existing technologies face challenges in preventing damage from etchants and minimizing voids or seams in gate electrodes during the formation process.
Innovation Solution
The implementation of a semiconductor device with protective patterns, including oxidized silicon, that surround the gate electrodes and extend between interlayer insulating layers, reducing the vertical width of the gate electrodes and preventing etchant damage, while also forming a gap-fill pattern and channel pattern to minimize voids and seams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protective patterns are added to prevent etchant damage, then reliability is improved, but device complexity increases
Solution Approach 1:
Protective patterns are formed on the gate electrode surfaces before the etching process to prevent etchant damage. The protective patterns include oxide layers and nitride layers that are deposited in advance to create a barrier against etchant penetration, thereby protecting the gate electrode from damage during subsequent etching steps.
Solution Approach 2:
The protective pattern uses composite material structure consisting of multiple layers including oxide layers (such as silicon oxide) and nitride layers (such as silicon nitride). This composite structure provides both chemical resistance to etchants and mechanical protection, combining the advantages of different materials to achieve superior protection while managing complexity.
2Manufacturing precision
If gate electrode width is reduced vertically, then manufacturing precision is improved, but voids and seams increase
Solution Approach 1:
The gate electrode width is reduced vertically only in specific regions where protective patterns are present, while maintaining full width in other regions. This local quality approach allows precise dimensional control in critical areas without compromising the overall structural integrity and prevents void formation by maintaining adequate width in non-critical regions.
Solution Approach 2:
Protective patterns are formed on the gate electrode surfaces before the etching process to prevent etchant damage. The protective patterns include oxide layers and nitride layers that are deposited in advance to create a barrier against etchant penetration, thereby protecting the gate electrode from damage during subsequent etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents damage from etchants and reduces or eliminates voids and seams in the gate electrodes, enhancing the structural integrity and performance of the semiconductor device.
Implementation Method 1
a tunneling layer in contact with the channel pattern
Implementation Method 2
a charge trap layer in contact with the tunneling layer
Data Source
AI summary
According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.