Semiconductor Gate Electrode Sidewall Verticality Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing is forming a gate electrode with a vertically oriented sidewall using anisotropic etching, as the etching rate of silicon films varies with impurity doping, leading to potential voids during dielectric film embedding due to constriction formation in the film thickness direction.
Innovation Solution
A manufacturing method involving a silicon film with varying impurity densities, where the center portion has a higher impurity density than the upper and lower portions, is used. A mask pattern is formed, and recesses are etched in the film, followed by oxidation and selective etching to control the width and shape, preventing constriction by ensuring the center portion remains wider than the upper and lower portions during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If anisotropic etching is used to form a gate electrode, then the sidewall can be made vertical to the substrate, but the etching rate varies with impurity doping causing constriction and void formation
Solution Approach 1:
The patent applies local quality by creating a silicon film with non-uniform impurity distribution, where the center portion has higher impurity density than the upper and lower portions. This localized variation in material properties ensures that the center etches faster than the edges during anisotropic etching, preventing constriction and maintaining a uniform width throughout the film thickness direction.
2Ease of manufacture
If the etching rate varies with impurity doping amount, then selective etching can be achieved, but constriction forms in the center portion during processing
Solution Approach 1:
The patent utilizes parameter changes by deliberately varying the impurity concentration profile within the silicon film thickness direction. The center portion is doped with higher impurity density compared to the upper and lower portions, which changes the etching rate parameter locally. This parameter variation enables the center to etch faster, counteracting the natural tendency toward constriction and achieving the desired shape control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents constriction and void formation by maintaining the center portion's width, facilitating accurate etching and embedding of dielectric films, enhancing the manufacturing process for semiconductor devices like NAND flash memories.
Implementation Method 1
a silicon oxide film is formed on a surface of the recess by an oxidation process of the silicon film
Data Source
AI summary
According to one embodiment, a silicon film, in which an impurity density of a center portion is higher than that of an upper portion and a lower portion, is formed above a base layer, a mask pattern is formed above the silicon film, a recess is formed in the silicon film by selectively etching the silicon film through the mask pattern, a silicon oxide film is formed on a surface of the recess by an oxidation process of the silicon film, and the silicon film under the recess is etched through the mask pattern after the oxidation process.