VG NAND Bit Line Pad Conductivity via Segmented Ion Implantation
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face challenges in isolating word line nodes and doping semiconductor structures due to stacked layers masking each other during ion implantation, making it difficult to achieve conductive bit line pads and source/drain regions, especially in vertical gate NAND (VG NAND) structures.
Innovation Solution
The proposed solution involves a layout that facilitates sidewall ion implantation by allowing regions implanted from positive and negative y-directions to naturally overlap, forming a connected n-type region throughout the bit line pad, ensuring permanent conductivity and reducing the need for additional measures to decrease bit line pad resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sidewall ion implantation is performed on bit line pads in VG NAND structures, then regions implanted from positive and negative y-directions can overlap to form connected n-type regions, but the stacked layers mask each other during ion implantation making it difficult to achieve conductive bit line pads
Solution Approach 1:
The bit line pad region is segmented into multiple implantation zones that are approached from different directions (positive and negative y-directions). Each zone is independently implanted to ensure complete coverage despite masking effects from stacked layers, ultimately forming a connected conductive region through the segmentation and overlap of these implanted zones.
2Reliability
If junction-free source/drain scheme is applied to semiconducting regions near transistor gates, then conductivity is induced when transistors are turned on, but bit line pads require permanent conductivity even when adjacent transistors are turned off
Solution Approach 1:
Different conductivity characteristics are applied to different regions: the bit line pad region receives ion implantation to create permanent conductivity, while the source/drain regions near transistor gates use the junction-free scheme that induces conductivity only when transistors are active. This local differentiation allows each region to have the specific conductivity property required for its function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the conductivity of bit line pads and source/drain regions, maintaining a continuous conductive path even when adjacent transistors are turned off, thereby improving the performance and efficiency of VG NAND flash memory devices.
Implementation Method 1
The layout facilitates sidewall ion implant processes, as regions which are implanted from a positive y-direction and a negative y-direction naturally overlap with each other
Data Source
AI summary
A non-volatile memory device, including: a substrate; a plurality of string stacks disposed over the substrate, each string stack including a long axis and a short axis in a plane parallel to the substrate, the long axis extending along a y-direction and the short axis extending along an x-direction, each string stack including a plurality of strings being stacked in a direction vertical to the substrate and having a first end and a second end at different locations in the y-direction, the plurality of string stacks including a first and a second set of string stacks, at least some of the string stacks of the first set of string stacks being offset along the x-direction from at least some of the string stacks of the second set of string stacks.