Vertical Memory Cell Charge Trap Segmentation for Interference Suppression
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Solution Overview
Problem
In highly scaled vertical memory devices, the increased density of memory cells leads to reduced reliability due to charge diffusion between adjacent cells, causing interference even with small intervals between them.
Innovation Solution
The integration of word line structures, insulating structures, channel films, and charge trap patterns with local insulating regions and air-gaps in a vertical direction, allowing for efficient suppression of cell interference by maintaining reliability even with small cell intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the interval between vertically adjacent cells is reduced to increase cell density, then storage capacity increases, but charge diffusion between adjacent cells causes interference and reduces reliability
Solution Approach 1:
The charge trap layer is segmented into multiple discrete charge trap patterns along the channel hole, with insulating regions separating adjacent patterns. This segmentation prevents charge diffusion between adjacent memory cells while maintaining high vertical cell density, thus resolving the contradiction between increased cell density and maintained reliability
Solution Approach 2:
Insulating regions are locally introduced between adjacent charge trap patterns in the vertical direction. These local insulating structures create electrical isolation only where needed (between adjacent cells) while maintaining conductivity within each cell, enabling high density without compromising reliability
2Reliability
If insulating structures are introduced between word line structures to suppress charge diffusion, then cell interference is reduced, but device complexity increases
Solution Approach 1:
The insulating structures serving charge isolation functions are merged with the word line structure stack in the vertical direction. The insulating regions are integrated between the charge trap patterns that are themselves part of the vertical stack, creating a unified structure that performs multiple functions (charge trapping, isolation, and word line formation) without proportionally increasing complexity
Solution Approach 2:
The vertical stack structure serves multiple functions: word line structures provide gate control, charge trap patterns provide charge storage, and insulating regions provide electrical isolation. This multi-functional integration allows the device to suppress cell interference while maintaining relatively simple manufacturing processes
Data Source
AI summary
An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween.