NVM and Logic Transistor Integration via Selective Gate Recessing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, the integration of logic transistors and non-volatile memory (NVM) cells faces challenges in achieving high performance without sacrificing logic performance or increasing costs, particularly in the context of the gate last process, where chemical mechanical polishing (CMP) can degrade isolation between control and select gates.
Innovation Solution
The solution involves recessing the control and select gates relative to the charge storage layer using a selective etch that targets polysilicon, thereby improving isolation and performance by removing polysilicon particles left from the CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used in the gate last process, then planarity and surface finish are improved, but isolation between control and select gates is degraded due to polysilicon particles
Solution Approach 1:
A polysilicon removal step is performed before the CMP process to eliminate polysilicon particles that would otherwise be generated during polishing. This preliminary action prevents the formation of harmful particles while still allowing CMP to achieve the desired surface planarity for the gate last process.
Solution Approach 2:
The polysilicon particles that are normally considered harmful contaminants are addressed by converting the harm into a controlled removal process. By selectively removing polysilicon before CMP, the process transforms a potential contamination problem into a controlled preparation step that enables both good surface finish and maintained gate isolation.
2Reliability
If gate last process is used to enhance logic transistor performance, then logic performance is improved, but additional process steps increase manufacturing cost
Solution Approach 1:
The gate last process steps are merged with the NVM fabrication sequence, allowing both logic transistors and NVM cells to share common process steps. This integration reduces the total number of additional process steps required compared to separate fabrication approaches, thereby lowering manufacturing costs while maintaining performance benefits.
Solution Approach 2:
The gate last process is designed to serve dual purposes: forming high-performance logic transistors and creating NVM cells with charge storage layers. This multi-functionality allows a single process sequence to deliver performance improvements for both device types, reducing the need for additional specialized process steps and associated costs.
3Reliability
If high-k gate dielectric is used to improve NVM performance, then memory performance is enhanced, but process compatibility with logic transistors becomes more difficult
Solution Approach 1:
Different gate dielectric materials are used in different regions of the semiconductor device. High-k dielectric is applied specifically to the NVM cell regions where it is needed for performance, while logic transistor regions use conventional dielectric materials. This localized approach allows each region to have optimized properties without requiring the entire fabrication process to be redesigned for high-k compatibility.
Solution Approach 2:
The semiconductor device is divided into distinct regions (NVM cells and logic transistors) that can be processed independently to some extent. This segmentation allows the high-k gate dielectric to be formed and processed specifically for NVM regions without adversely affecting logic transistor fabrication, thereby maintaining process compatibility across different device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the isolation between the select and control gates, thereby improving the performance of both logic and NVM cells while maintaining cost-effectiveness by preventing the adverse effects of CMP on gate isolation.
Implementation Method 1
The solution involves recessing the control and select gates relative to the charge storage layer using a selective etch that targets polysilicon, thereby improving isolation and performance by removing polysilicon particles left from the CMP process
Data Source
AI summary
A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.