Semiconductor Memory Word Line Voltage Control for Fast Charging
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high-speed operations due to increased wiring resistance and parasitic capacitance resulting from reduced Z-direction widths of conductive layers, which can lead to longer charging times and potential write errors.
Innovation Solution
The semiconductor memory device employs a specific voltage control strategy during the write operation, where the voltage of the selected word line is initially increased to a value larger than the program voltage plus a delta voltage, then decreased to the program voltage, and maintained at this level to ensure efficient charge storage and prevent write errors, while adjusting the delta voltage and loop number to optimize charging speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the Z-direction width of conductive layers is reduced to increase integration density, then device integration is improved, but wiring resistance and parasitic capacitance increase leading to longer charging times
Solution Approach 1:
The patent applies preliminary action by pre-charging the selected word line to a voltage higher than the standard program voltage before actual programming begins. This advance preparation ensures that when programming operations start, the word line is already at the required voltage level, eliminating delays during the programming process and compensating for the increased RC time constants caused by reduced conductive layer widths.
2Quantity of substance
If the Z-direction width of conductive layers is reduced to increase integration density, then device integration is improved, but wiring resistance increases leading to potential write errors
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging the selected word line to a voltage higher than the standard program voltage before programming operations begin. This advance voltage preparation counteracts the voltage drops that would occur during programming due to increased wiring resistance in the reduced Z-direction width structure, preventing write errors and ensuring reliable programming operations.
3Speed
If the voltage of the selected word line is increased to a value larger than the program voltage, then charging speed is improved, but voltage control complexity increases
Solution Approach 1:
The patent applies dynamics by implementing a two-stage voltage control strategy: first charging the selected word line to a higher voltage than the standard program voltage to accelerate charging speed, then reducing it to the standard program voltage level for the actual programming operation. This dynamic voltage adjustment optimizes both charging speed and programming accuracy while managing voltage control complexity through a structured approach.
Data Source
AI summary
A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.